diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-04-17 10:43:57 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-04-17 10:45:23 +0800 |
| commit | 30596ec32e2cd141d73ee8701386887def9e98c0 (patch) | |
| tree | c8b0d725c46fd8fa504ec0bf41c92c6ff680b406 /include/uapi/linux/serial_core.h | |
| parent | d54e79340ff8d65b6c63ac278158add2fe211fd0 (diff) | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
Back merge 'drm-intel-fixes' into gvt-fixes
Need for 4.17-rc1
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'include/uapi/linux/serial_core.h')
| -rw-r--r-- | include/uapi/linux/serial_core.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 1c8413f93e3d..dce5f9dae121 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -76,6 +76,9 @@ #define PORT_SUNZILOG 38 #define PORT_SUNSAB 39 +/* Nuvoton UART */ +#define PORT_NPCM 40 + /* Intel EG20 */ #define PORT_PCH_8LINE 44 #define PORT_PCH_2LINE 45 |