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| author | Christophe Leroy (CS GROUP) <chleroy@kernel.org> | 2026-01-07 17:59:10 +0100 |
|---|---|---|
| committer | Christophe Leroy (CS GROUP) <chleroy@kernel.org> | 2026-01-10 10:56:21 +0100 |
| commit | 0d069bb381839ba252ecca4031f7eb6f2fc72ab4 (patch) | |
| tree | 9bcbef0c14b5d9c05c1bfaf68cc845343da7cc5e /include | |
| parent | f0bcd784e1b76bc3918433f2bd7e52f56f0dcf22 (diff) | |
dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
The QUICC Engine provides interrupts for a few I/O ports. This is
handled via a separate interrupt ID and managed via a triplet of
dedicated registers hosted by the SoC.
Implement an interrupt driver for it so that those IRQs can then
be linked to the related GPIOs.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/7708243d6cca21004de8b3da87369c06dbee3848.1767804922.git.chleroy@kernel.org
Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
[moved from bindings/soc/fsl/cpm_qe/ to bindings/interrupt-controller/ while applying]
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions