Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Here's the clk changes for the merge window which is dominated in the
  diffstat by Qualcomm churning out new SoCs that need clk drivers.

  Looking beyond the sheer amount of lines of mostly data there we have
  a clk nexus DT binding change in the core clk framework and a driver
  core patch to add a subsys driver macro.

  The clock nexus support is useful for devices that map clks internally
  or for connectors on a board that route clock signals to another
  board. I suspect the use of this will expand in the future, so we have
  unit tests to make sure it doesn't break.

  The driver core change adds subsys_driver() and
  subsys_platform_driver() so we can register early drivers without
  open-coding that all (module_platform_driver() is at device initcall
  level so it isn't be used).

  Beyond the core framework bits we have lots of changes all over the
  tree to initialize 'struct clk_init_data'. The potential risk here is
  that someone forgets to initialize all the members of that structure
  and either the clk flags cause weird behavior later on or the parents
  are pointing at junk and the clk is orphaned forever. The patches just
  initialize the thing with zeroes to be safe. Longer term we should
  probably move this struct out of 'struct clk_hw' and pass it during
  clk registration time. That's a much bigger change and would require
  restructuring entire drivers that rely on the pointer being there.

  Finally, we have the usual fixes like calculation updates for
  dividers, handling error paths during clk registration, or fixing clk
  data now that drivers are using them. Those patches are dwarfed by the
  amount of new SoC support and only affect those SoCs and the consumers
  of those clks. Overall I'm more concerned the clk_init_data patches
  are going to expose some latent bugs that we didn't notice before
  because something was relying on clks being orphaned and now they're
  not.

  Core:
   - subsys_driver() / subsys_platform_driver() macros
   - Clock nexus DT binding support (with KUnit tests)
   - Spread-spectrum configuration validation
   - Fully initialize struct clk_init_data across many drivers

  New Drivers:
   - Anlogic DR1V90 CRU
   - ZTE zx297520v3 top, matrix, and LSP clocks
   - Samsung Exynos5515 and ACPM driver extended to Exynos850.
   - Qualcomm Eliza camera, camera-BIST, GPU, and video clks
   - Qualcomm Hawi / Maili camera and GPU controllers
   - Qualcomm Kuno global, RPMh
   - Qualcomm MSM8952 global, RPM
   - Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets
   - Qualcomm IPQ5210 / IPQ9650 network clocks
   - i.MX93 350 MHz fractional-N GP-PLL for display
   - i.MX pll14xx spread-spectrum clock generation
   - Amlogic A9 SCMI clock controller
   - Allwinner single-divider "update bit" support
   - EN7523 Serdes port selection"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (316 commits)
  clk: imx: pll14xx: support spread spectrum clock generation
  clk: cdce925: Size the PLL child name buffer for any int
  clk: stm32: fix clock array size for STM32MP21
  dt-bindings: clock: Convert HiSilicon clocks to DT schema
  clk: lmk04832: Handle reset GPIO lookup errors
  dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
  clk: tegra: bpmp: remove kcalloc
  clk: mmp2-audio: add missing PM_CLK dependency
  clk: zte: Introduce a driver for zx297520v3 LSP clocks
  clk: zte: Introduce a driver for zx297520v3 matrix clocks
  clk: zte: Introduce a driver for zx297520v3 top clocks
  clk: zte: Add zx PLL support infrastructure
  clk: zte: Add regmap-based clocks
  clk: zte: Add Clock registration infrastructure
  dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
  clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
  ...

21 files changed, 1010 insertions, 7 deletions

diff --git a/include/dt-bindings/clock/amlogic,a9-scmi-clkc.h b/include/dt-bindings/clock/amlogic,a9-scmi-clkc.h
new file mode 100644
index 000000000000..d543db9fe035
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,a9-scmi-clkc.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AMLOGIC_A9_SCMI_CLKC_H
+#define __AMLOGIC_A9_SCMI_CLKC_H
+
+#define CLKID_GP0_PLL_OSC			0
+#define CLKID_GP1_PLL_OSC			1
+#define CLKID_HIFI_PLL_OSC			2
+#define CLKID_GP2_PLL_OSC			3
+#define CLKID_MCLK_PLL_OSC			4
+#define CLKID_FIXED_PLL				5
+#define CLKID_FCLK_50M_PREDIV			6
+#define CLKID_FCLK_50M_DIV			7
+#define CLKID_FCLK_50M				8
+#define CLKID_FCLK_DIV2_DIV			9
+#define CLKID_FCLK_DIV2				10
+#define CLKID_FCLK_DIV2P5_DIV			11
+#define CLKID_FCLK_DIV2P5			12
+#define CLKID_FCLK_DIV3_DIV			13
+#define CLKID_FCLK_DIV3				14
+#define CLKID_FCLK_DIV4_DIV			15
+#define CLKID_FCLK_DIV4				16
+#define CLKID_FCLK_DIV5_DIV			17
+#define CLKID_FCLK_DIV5				18
+#define CLKID_FCLK_DIV7_DIV			19
+#define CLKID_FCLK_DIV7				20
+#define CLKID_SYS_CLK				21
+#define CLKID_SYS_AO_SYS			22
+#define CLKID_SYS_MMC_APB			23
+#define CLKID_SYS_CPU_APB			24
+#define CLKID_SYS_GIC				25
+#define CLKID_AXI_CLK				26
+#define CLKID_AXI_SYS_NIC			27
+#define CLKID_AXI_RAMA				28
+#define CLKID_CPU_CLK				29
+#define CLKID_A78_CLK				30
+#define CLKID_DSU_CLK				31
+#define CLKID_ACLKM				32
+#define CLKID_GP1_PLL				33
+#define CLKID_GP2_PLL				34
+#define CLKID_SYS_PLL_DIV16			35
+#define CLKID_CPU_CLK_DIV16			36
+#define CLKID_A78_CLK_DIV16			37
+#define CLKID_DSU_CLK_DIV16			38
+#define CLKID_GIC_CLK				39
+#define CLKID_RTC				40
+
+#endif /* __AMLOGIC_A9_SCMI_CLKC_H */
diff --git a/include/dt-bindings/clock/anlogic,dr1v90-cru.h b/include/dt-bindings/clock/anlogic,dr1v90-cru.h
new file mode 100644
index 000000000000..664daf3946a7
--- /dev/null
+++ b/include/dt-bindings/clock/anlogic,dr1v90-cru.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2024-2025 Anlogic, Inc.
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ANLOGIC_DR1V90_CRU_H_
+#define _DT_BINDINGS_CLOCK_ANLOGIC_DR1V90_CRU_H_
+
+#define CLK_OSC_DIV2		0
+#define CLK_CPU_PLL		1
+#define CLK_CPU_PLL_4X		2
+#define CLK_CPU_4X		3
+#define CLK_CPU_2X		4
+#define CLK_CPU_1X		5
+#define CLK_IO_PLL		6
+#define CLK_IO_1000M		7
+#define CLK_IO_400M		8
+#define CLK_IO_25M		9
+#define CLK_IO_80M		10
+#define CLK_IO_400M_DIV2	11
+#define CLK_IO_400M_DIV4	12
+#define CLK_IO_400M_DIV8	13
+#define CLK_IO_400M_DIV16	14
+#define CLK_QSPI		15
+#define CLK_SPI			16
+#define CLK_SMC			17
+#define CLK_SDIO		18
+#define CLK_GPIO_DB		19
+#define CLK_EFUSE		20
+#define CLK_TVS			21
+#define CLK_TRNG		22
+#define CLK_OSC_DIV		23
+#define CLK_PWM			24
+#define CLK_FCLK0		25
+#define CLK_FCLK1		26
+#define CLK_FCLK2		27
+#define CLK_FCLK3		28
+#define CLK_WDT_SEL		29
+#define CLK_EFUSE_SEL		30
+#define CLK_CAN_SEL		31
+#define CLK_CPU_SEL		32
+#define CLK_CAN0		33
+#define CLK_CAN1		34
+
+#endif /* _DT_BINDINGS_CLOCK_ANLOGIC_DR1V90_CRU_H_ */
diff --git a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h
index ba2d70f776a6..764d837d6162 100644
--- a/include/dt-bindings/clock/nuvoton,ma35d1-clk.h
+++ b/include/dt-bindings/clock/nuvoton,ma35d1-clk.h
@@ -248,6 +248,7 @@
 #define ADC_GATE	233
 #define EADC_DIV	234
 #define EADC_GATE	235
-#define	CLK_MAX_IDX	236
+#define PCLK3_DIV4096	236
+#define PCLK4_DIV4096	237
 
 #endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8952.h b/include/dt-bindings/clock/qcom,gcc-msm8952.h
new file mode 100644
index 000000000000..5b5c38a9f4dd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8952.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2020 Linaro Limited
+ * Copyright 2026 Muzaffer Kadir <muzafferkadir@mainlining.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8952_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8952_H
+
+#define GPLL0						0
+#define GPLL0_VOTE					1
+#define GPLL3						2
+#define GPLL3_EARLY					3
+#define GPLL4						4
+#define GPLL4_VOTE					5
+#define GPLL6						6
+#define GPLL6_VOTE					7
+#define CAMSS_TOP_AHB_CLK_SRC				8
+#define APSS_AHB_CLK_SRC				9
+#define CSI0_CLK_SRC					10
+#define CSI1_CLK_SRC					11
+#define GFX3D_CLK_SRC					12
+#define VFE0_CLK_SRC					13
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			14
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			15
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			16
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			17
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC			18
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC			19
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC			20
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC			21
+#define BLSP1_UART1_APPS_CLK_SRC			22
+#define BLSP1_UART2_APPS_CLK_SRC			23
+#define CCI_CLK_SRC					24
+#define CAMSS_GP0_CLK_SRC				25
+#define CAMSS_GP1_CLK_SRC				26
+#define JPEG0_CLK_SRC					27
+#define MCLK0_CLK_SRC					28
+#define MCLK1_CLK_SRC					29
+#define CSI0PHYTIMER_CLK_SRC				30
+#define CSI1PHYTIMER_CLK_SRC				31
+#define CPP_CLK_SRC					32
+#define CRYPTO_CLK_SRC					33
+#define GP1_CLK_SRC					34
+#define GP2_CLK_SRC					35
+#define GP3_CLK_SRC					36
+#define BYTE0_CLK_SRC					37
+#define ESC0_CLK_SRC					38
+#define MDP_CLK_SRC					39
+#define PCLK0_CLK_SRC					40
+#define VSYNC_CLK_SRC					41
+#define PDM2_CLK_SRC					42
+#define SDCC1_APPS_CLK_SRC				43
+#define SDCC2_APPS_CLK_SRC				44
+#define USB_HS_SYSTEM_CLK_SRC				45
+#define VCODEC0_CLK_SRC					46
+#define GCC_BLSP1_AHB_CLK				47
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			48
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			49
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			50
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			51
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK			52
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK			53
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK			54
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK			55
+#define GCC_BLSP1_UART1_APPS_CLK			56
+#define GCC_BLSP1_UART2_APPS_CLK			57
+#define GCC_BOOT_ROM_AHB_CLK				58
+#define GCC_CAMSS_CCI_AHB_CLK				59
+#define GCC_CAMSS_CCI_CLK				60
+#define GCC_CAMSS_CSI0_AHB_CLK				61
+#define GCC_CAMSS_CSI0_CLK				62
+#define GCC_CAMSS_CSI0PHY_CLK				63
+#define GCC_CAMSS_CSI0PIX_CLK				64
+#define GCC_CAMSS_CSI0RDI_CLK				65
+#define GCC_CAMSS_CSI1_AHB_CLK				66
+#define GCC_CAMSS_CSI1_CLK				67
+#define GCC_CAMSS_CSI1PHY_CLK				68
+#define GCC_CAMSS_CSI1PIX_CLK				69
+#define GCC_CAMSS_CSI1RDI_CLK				70
+#define GCC_CAMSS_CSI_VFE0_CLK				71
+#define GCC_CAMSS_GP0_CLK				72
+#define GCC_CAMSS_GP1_CLK				73
+#define GCC_CAMSS_ISPIF_AHB_CLK				74
+#define GCC_CAMSS_JPEG0_CLK				75
+#define GCC_CAMSS_JPEG_AHB_CLK				76
+#define GCC_CAMSS_JPEG_AXI_CLK				77
+#define GCC_CAMSS_MCLK0_CLK				78
+#define GCC_CAMSS_MCLK1_CLK				79
+#define GCC_CAMSS_MICRO_AHB_CLK				80
+#define GCC_CAMSS_CSI0PHYTIMER_CLK			81
+#define GCC_CAMSS_CSI1PHYTIMER_CLK			82
+#define GCC_CAMSS_AHB_CLK				83
+#define GCC_CAMSS_TOP_AHB_CLK				84
+#define GCC_CAMSS_CPP_AHB_CLK				85
+#define GCC_CAMSS_CPP_CLK				86
+#define GCC_CAMSS_VFE0_CLK				87
+#define GCC_CAMSS_VFE0_AHB_CLK				88
+#define GCC_CAMSS_VFE0_AXI_CLK				89
+#define GCC_CRYPTO_AHB_CLK				90
+#define GCC_CRYPTO_AXI_CLK				91
+#define GCC_CRYPTO_CLK					92
+#define GCC_OXILI_GMEM_CLK				93
+#define GCC_GP1_CLK					94
+#define GCC_GP2_CLK					95
+#define GCC_GP3_CLK					96
+#define GCC_MDSS_AHB_CLK				97
+#define GCC_MDSS_AXI_CLK				98
+#define GCC_MDSS_BYTE0_CLK				99
+#define GCC_MDSS_ESC0_CLK				100
+#define GCC_MDSS_MDP_CLK				101
+#define GCC_MDSS_PCLK0_CLK				102
+#define GCC_MDSS_VSYNC_CLK				103
+#define GCC_MSS_CFG_AHB_CLK				104
+#define GCC_OXILI_AHB_CLK				105
+#define GCC_OXILI_GFX3D_CLK				106
+#define GCC_PDM2_CLK					107
+#define GCC_PDM_AHB_CLK					108
+#define GCC_PRNG_AHB_CLK				109
+#define GCC_SDCC1_AHB_CLK				110
+#define GCC_SDCC1_APPS_CLK				111
+#define GCC_SDCC2_AHB_CLK				112
+#define GCC_SDCC2_APPS_CLK				113
+#define GCC_GTCU_AHB_CLK				114
+#define GCC_JPEG_TBU_CLK				115
+#define GCC_MDP_TBU_CLK					116
+#define GCC_SMMU_CFG_CLK				117
+#define GCC_VENUS_TBU_CLK				118
+#define GCC_VFE_TBU_CLK					119
+#define GCC_USB2A_PHY_SLEEP_CLK				120
+#define GCC_USB_HS_AHB_CLK				121
+#define GCC_USB_HS_SYSTEM_CLK				122
+#define GCC_VENUS0_AHB_CLK				123
+#define GCC_VENUS0_AXI_CLK				124
+#define GCC_VENUS0_VCODEC0_CLK				125
+#define GCC_APSS_TCU_CLK				126
+#define GCC_GFX_TCU_CLK					127
+#define GCC_BIMC_GFX_CLK				128
+#define GCC_BIMC_GPU_CLK				129
+#define GCC_MSS_Q6_BIMC_AXI_CLK				130
+#define GCC_GFX_TBU_CLK					131
+#define GCC_CPP_TBU_CLK					132
+#define USB_FS_SYSTEM_CLK_SRC				133
+#define USB_FS_IC_CLK_SRC				134
+#define GCC_USB_FS_AHB_CLK				135
+#define GCC_USB_FS_IC_CLK				136
+#define GCC_USB_FS_SYSTEM_CLK				137
+#define GCC_VENUS0_CORE0_VCODEC0_CLK			138
+#define GCC_VENUS0_CORE1_VCODEC0_CLK			139
+#define GCC_OXILI_TIMER_CLK				140
+#define GCC_USB_HS_PHY_CFG_AHB_CLK			141
+#define CSI2_CLK_SRC					142
+#define GCC_CAMSS_CSI2_AHB_CLK				143
+#define GCC_CAMSS_CSI2_CLK				144
+#define GCC_CAMSS_CSI2PHY_CLK				145
+#define GCC_CAMSS_CSI2PIX_CLK				146
+#define GCC_CAMSS_CSI2RDI_CLK				147
+#define SDCC1_ICE_CORE_CLK_SRC				148
+#define GCC_SDCC1_ICE_CORE_CLK				149
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC			150
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC			151
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC			152
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC			153
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC			154
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC			155
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC			156
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC			157
+#define BLSP2_UART1_APPS_CLK_SRC			158
+#define BLSP2_UART2_APPS_CLK_SRC			159
+#define GCC_BLSP2_AHB_CLK				160
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK			161
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK			162
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK			163
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK			164
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK			165
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK			166
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK			167
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK			168
+#define GCC_BLSP2_UART1_APPS_CLK			169
+#define GCC_BLSP2_UART2_APPS_CLK			170
+#define VFE1_CLK_SRC					171
+#define GCC_CAMSS_VFE1_CLK				172
+#define GCC_CAMSS_VFE1_AHB_CLK				173
+#define GCC_CAMSS_VFE1_AXI_CLK				174
+#define GCC_CAMSS_CSI_VFE1_CLK				175
+#define MCLK2_CLK_SRC					176
+#define GCC_CAMSS_MCLK2_CLK				177
+#define GCC_VFE1_TBU_CLK				178
+#define GCC_IPA_TBU_CLK					179
+#define GCC_CAMSS_CPP_AXI_CLK				180
+
+/* Indexes for GDSCs */
+#define VENUS_GDSC				0
+#define MDSS_GDSC				1
+#define JPEG_GDSC				2
+#define VFE0_GDSC				3
+#define VFE1_GDSC				4
+#define OXILI_GX_GDSC				5
+#define VENUS_CORE0_GDSC			6
+#define VENUS_CORE1_GDSC			7
+#define CPP_GDSC				8
+
+/* Indexes for Resets */
+#define GCC_CRYPTO_BCR				0
+#define GCC_USB_FS_BCR				1
+#define GCC_USB_HS_BCR				2
+#define GCC_QUSB2_PHY_BCR			3
+#define GCC_USB2_HS_PHY_ONLY_BCR		4
+#define GCC_SDCC1_BCR				5
+#define GCC_SDCC2_BCR				6
+#define GCC_MDSS_BCR				7
+#define GCC_CAMSS_MICRO_BCR			8
+#define GCC_MSS_BCR				9
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h
new file mode 100644
index 000000000000..9201d1e1062c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H
+
+/* Parent clock */
+#define IPQ5210_CMN_PLL_CLK		0
+
+/* Fixed-rate clocks */
+#define IPQ5210_XO_24MHZ_CLK		1
+#define IPQ5210_SLEEP_32KHZ_CLK		2
+
+/* Configurable divider clocks */
+#define IPQ5210_NSS_CLK			3
+#define IPQ5210_PPE_CLK			4
+#define IPQ5210_PON_CLK			5
+#define IPQ5210_EPHY_RAW_CLK		6
+
+/* Gate clocks */
+#define IPQ5210_PCS_31P25MHZ_CLK	7
+#define IPQ5210_ETH0_50MHZ_CLK		8
+#define IPQ5210_ETH1_50MHZ_CLK		9
+#define IPQ5210_ETH2_50MHZ_CLK		10
+#define IPQ5210_EPHY_50MHZ_CLK		11
+#define IPQ5210_ETH_25MHZ_CLK		12
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,kuno-gcc.h b/include/dt-bindings/clock/qcom,kuno-gcc.h
new file mode 100644
index 000000000000..a237b25a061d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,kuno-gcc.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KUNO_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_KUNO_H
+
+/* GCC clocks */
+#define GPLL0							0
+#define GPLL0_OUT_EVEN						1
+#define GPLL2							2
+#define GPLL3							3
+#define GPLL4							4
+#define GPLL4_OUT_EVEN						5
+#define GCC_EMAC0_AXI_CLK					7
+#define GCC_EMAC0_PHY_AUX_CLK					8
+#define GCC_EMAC0_PHY_AUX_CLK_SRC				9
+#define GCC_EMAC0_PTP_CLK					10
+#define GCC_EMAC0_PTP_CLK_SRC					11
+#define GCC_EMAC0_RGMII_CLK					12
+#define GCC_EMAC0_RGMII_CLK_SRC					13
+#define GCC_EMAC0_SLV_AHB_CLK					14
+#define GCC_EMAC_0_CLKREF_EN					15
+#define GCC_GP1_CLK						16
+#define GCC_GP1_CLK_SRC						17
+#define GCC_GP2_CLK						18
+#define GCC_GP2_CLK_SRC						19
+#define GCC_GP3_CLK						20
+#define GCC_GP3_CLK_SRC						21
+#define GCC_PCIE_0_CLKREF_EN					22
+#define GCC_PCIE_AUX_CLK					23
+#define GCC_PCIE_AUX_CLK_SRC					24
+#define GCC_PCIE_AUX_PHY_CLK_SRC				25
+#define GCC_PCIE_CFG_AHB_CLK					26
+#define GCC_PCIE_MSTR_AXI_CLK					27
+#define GCC_PCIE_PIPE_CLK					28
+#define GCC_PCIE_PIPE_CLK_SRC					29
+#define GCC_PCIE_RCHNG_PHY_CLK					30
+#define GCC_PCIE_RCHNG_PHY_CLK_SRC				31
+#define GCC_PCIE_SLEEP_CLK					32
+#define GCC_PCIE_SLV_AXI_CLK					33
+#define GCC_PCIE_SLV_Q2A_AXI_CLK				34
+#define GCC_PDM2_CLK						35
+#define GCC_PDM2_CLK_SRC					36
+#define GCC_PDM_AHB_CLK						37
+#define GCC_PDM_XO4_CLK						38
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				39
+#define GCC_QUPV3_WRAP0_CORE_CLK				40
+#define GCC_QUPV3_WRAP0_S0_CLK					41
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				42
+#define GCC_QUPV3_WRAP0_S1_CLK					43
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				44
+#define GCC_QUPV3_WRAP0_S2_CLK					45
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				46
+#define GCC_QUPV3_WRAP0_S3_CLK					47
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				48
+#define GCC_QUPV3_WRAP0_S4_CLK					49
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				50
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				51
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				52
+#define GCC_SDCC4_AHB_CLK					53
+#define GCC_SDCC4_APPS_CLK					54
+#define GCC_SDCC4_APPS_CLK_SRC					55
+#define GCC_SNOC_CNOC_USB3_CLK					56
+#define GCC_SYS_NOC_USB_SF_AXI_CLK				57
+#define GCC_USB20_MASTER_CLK					58
+#define GCC_USB20_MASTER_CLK_SRC				59
+#define GCC_USB20_MOCK_UTMI_CLK					60
+#define GCC_USB20_MOCK_UTMI_CLK_SRC				61
+#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC			62
+#define GCC_USB20_SLEEP_CLK					63
+#define GCC_USB2_CLKREF_EN					64
+#define GCC_USB3_PRIM_CLKREF_EN					65
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK				66
+#define GCC_BOOT_ROM_AHB_CLK					68
+
+/* GCC power domains */
+#define GCC_EMAC0_GDSC						0
+#define GCC_PCIE_GDSC						1
+#define GCC_USB20_GDSC						2
+
+/* GCC resets */
+#define GCC_EMAC0_BCR						0
+#define GCC_PCIE_BCR						1
+#define GCC_PCIE_LINK_DOWN_BCR					2
+#define GCC_PCIE_NOCSR_COM_PHY_BCR				3
+#define GCC_PCIE_PHY_BCR					4
+#define GCC_PCIE_PHY_CFG_AHB_BCR				5
+#define GCC_PCIE_PHY_COM_BCR					6
+#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR				7
+#define GCC_PDM_BCR						8
+#define GCC_QUPV3_WRAPPER_0_BCR					9
+#define GCC_QUSB2PHY_BCR					10
+#define GCC_SDCC4_BCR						11
+#define GCC_TCSR_PCIE_BCR					12
+#define GCC_USB20_BCR						13
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				14
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindings/clock/qcom,nord-negcc.h
index a7024317e90b..ad9ff389956d 100644
--- a/include/dt-bindings/clock/qcom,nord-negcc.h
+++ b/include/dt-bindings/clock/qcom,nord-negcc.h
@@ -121,5 +121,6 @@
 #define NE_GCC_USB3PHY_PHY_PRIM_BCR				11
 #define NE_GCC_USB3PHY_PHY_SEC_BCR				12
 #define NE_GCC_QUSB2PHY_PRIM_BCR				13
+#define NE_GCC_QUSB2PHY_SEC_BCR					14
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindings/clock/qcom,nord-segcc.h
index f0f7422af692..de4539b99985 100644
--- a/include/dt-bindings/clock/qcom,nord-segcc.h
+++ b/include/dt-bindings/clock/qcom,nord-segcc.h
@@ -84,6 +84,8 @@
 #define SE_GCC_QUPV3_WRAP1_S6_CLK				74
 #define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC				75
 #define SE_GCC_QUPV3_WRAP1_S_AHB_CLK				76
+#define SE_GCC_EMAC0_CNOC_APB_CLK				77
+#define SE_GCC_EMAC1_CNOC_APB_CLK				78
 
 /* SE_GCC power domains */
 #define SE_GCC_EMAC0_GDSC					0
diff --git a/include/dt-bindings/clock/qcom,qcs8300-gcc.h b/include/dt-bindings/clock/qcom,qcs8300-gcc.h
index a0083b1d2126..3c674c7baaba 100644
--- a/include/dt-bindings/clock/qcom,qcs8300-gcc.h
+++ b/include/dt-bindings/clock/qcom,qcs8300-gcc.h
@@ -191,6 +191,11 @@
 #define GCC_VIDEO_AXI0_CLK					181
 #define GCC_VIDEO_AXI1_CLK					182
 #define GCC_VIDEO_XO_CLK					183
+#define GCC_GPLL5						184
+#define GCC_TSCSS_AHB_CLK					185
+#define GCC_TSCSS_CNTR_CLK_SRC					186
+#define GCC_TSCSS_ETU_CLK					187
+#define GCC_TSCSS_GLOBAL_CNTR_CLK				188
 
 /* GCC power domains */
 #define GCC_EMAC0_GDSC						0
@@ -230,5 +235,6 @@
 #define GCC_VIDEO_BCR						26
 #define GCC_VIDEO_AXI0_CLK_ARES					27
 #define GCC_VIDEO_AXI1_CLK_ARES					28
+#define GCC_TSCSS_BCR						29
 
 #endif
diff --git a/include/dt-bindings/clock/samsung,exynos5515-cmu.h b/include/dt-bindings/clock/samsung,exynos5515-cmu.h
new file mode 100644
index 000000000000..2877d3681b55
--- /dev/null
+++ b/include/dt-bindings/clock/samsung,exynos5515-cmu.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2026 Aiden Isik <aidenisik+git@member.fsf.org>
+ * Author: Aiden Isik <aidenisik+git@member.fsf.org>
+ *
+ * Device Tree binding constants for Exynos5515 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS5515_H
+#define _DT_BINDINGS_CLOCK_EXYNOS5515_H
+
+/* CMU_TOP */
+#define CLK_FOUT_AUD_PLL			1
+#define CLK_FOUT_SHARED0_PLL			2
+#define CLK_FOUT_SHARED1_PLL			3
+
+#define CLK_MOUT_CMU_APM_BUS			4
+#define CLK_MOUT_CMU_CORE_BUS			5
+#define CLK_MOUT_CMU_CORE_SSS			6
+#define CLK_MOUT_CMU_CPUCL0_BUSP		7
+#define CLK_MOUT_CMU_CPUCL0_CPU			8
+#define CLK_MOUT_CMU_CPUCL0_DBG			9
+#define CLK_MOUT_CMU_DPU_AUDIF			10
+#define CLK_MOUT_CMU_DPU_AUD_BUS		11
+#define CLK_MOUT_CMU_DPU_AUD_CPU		12
+#define CLK_MOUT_CMU_DPU_BUS			13
+#define CLK_MOUT_CMU_FSYS_BUS			14
+#define CLK_MOUT_CMU_FSYS_MMC_CARD		15
+#define CLK_MOUT_CMU_FSYS_MMC_EMBD		16
+#define CLK_MOUT_CMU_FSYS_USB20DRD		17
+#define CLK_MOUT_CMU_G3D_BUS			18
+#define CLK_MOUT_CMU_MFC_BUS			19
+#define CLK_MOUT_CMU_MIF_BUSP			20
+#define CLK_MOUT_CMU_MIF_SWITCH			21
+#define CLK_MOUT_CMU_MODEM_SHARED1		22
+#define CLK_MOUT_CMU_PERI_BUS			23
+#define CLK_MOUT_CMU_PERI_IP			24
+#define CLK_MOUT_CMU_PERI_UART			25
+#define CLK_MOUT_CMU_CMUREF			26
+
+#define CLK_DOUT_AP2CP_SHARED0_PLL		27
+#define CLK_DOUT_AP2CP_SHARED1_PLL		28
+#define CLK_DOUT_AP2CP_SHARED2_PLL		29
+#define CLK_DOUT_CMU_APM_BUS			30
+#define CLK_DOUT_CMU_CMU_BOOST			31
+#define CLK_DOUT_CMU_CORE_BUS			32
+#define CLK_DOUT_CMU_CORE_SSS			33
+#define CLK_DOUT_CMU_CPUCL0_BUSP		34
+#define CLK_DOUT_CMU_CPUCL0_CPU			35
+#define CLK_DOUT_CMU_CPUCL0_DBG			36
+#define CLK_DOUT_CMU_DPU_AUDIF			37
+#define CLK_DOUT_CMU_DPU_AUD_BUS		38
+#define CLK_DOUT_CMU_DPU_AUD_CPU		39
+#define CLK_DOUT_CMU_DPU_BUS			40
+#define CLK_DOUT_CMU_FSYS_BUS			41
+#define CLK_DOUT_CMU_FSYS_MMC_CARD		42
+#define CLK_DOUT_CMU_FSYS_MMC_EMBD		43
+#define CLK_DOUT_CMU_FSYS_USB20DRD		44
+#define CLK_DOUT_CMU_G3D_BUS			45
+#define CLK_DOUT_CMU_MFC_BUS			46
+#define CLK_DOUT_CMU_MIF_BUSP			47
+#define CLK_DOUT_CMU_PERI_BUS			48
+#define CLK_DOUT_CMU_PERI_IP			49
+#define CLK_DOUT_CMU_PERI_UART			50
+#define CLK_DOUT_CMU_CMUREF			51
+
+#define CLK_DOUT_SHARED0_DIV2			52
+#define CLK_DOUT_SHARED0_DIV3			53
+#define CLK_DOUT_SHARED0_DIV4			54
+#define CLK_DOUT_SHARED1_DIV2			55
+#define CLK_DOUT_SHARED1_DIV3			56
+#define CLK_DOUT_SHARED1_DIV4			57
+#define CLK_DOUT_AUD_DIV2			58
+#define CLK_DOUT_AUD_DIV3			59
+#define CLK_DOUT_AUD_DIV4			60
+
+#define CLK_GOUT_CMU_MIF_SWITCH			61
+#define CLK_GOUT_CMU_APM_BUS			62
+#define CLK_GOUT_CMU_CORE_BUS			63
+#define CLK_GOUT_CMU_CORE_SSS			64
+#define CLK_GOUT_CMU_CPUCL0_BUSP		65
+#define CLK_GOUT_CMU_CPUCL0_CPU			66
+#define CLK_GOUT_CMU_CPUCL0_DBG			67
+#define CLK_GOUT_CMU_DPU_AUDIF			68
+#define CLK_GOUT_CMU_DPU_AUD_BUS		69
+#define CLK_GOUT_CMU_DPU_AUD_CPU		70
+#define CLK_GOUT_CMU_DPU_BUS			71
+#define CLK_GOUT_CMU_FSYS_BUS			72
+#define CLK_GOUT_CMU_FSYS_MMC_CARD		73
+#define CLK_GOUT_CMU_FSYS_MMC_EMBD		74
+#define CLK_GOUT_CMU_FSYS_USB20DRD		75
+#define CLK_GOUT_CMU_G3D_BUS			76
+#define CLK_GOUT_CMU_MFC_BUS			77
+#define CLK_GOUT_CMU_MIF_BUSP			78
+#define CLK_GOUT_CMU_MODEM_SHARED0		79
+#define CLK_GOUT_CMU_MODEM_SHARED1		80
+#define CLK_GOUT_CMU_MODEM_SHARED2		81
+#define CLK_GOUT_CMU_PERI_BUS			82
+#define CLK_GOUT_CMU_PERI_IP			83
+#define CLK_GOUT_CMU_PERI_UART			84
+
+/* CMU_PERI */
+#define CLK_MOUT_PLL_PERI_BUS_USER		1
+#define CLK_MOUT_PLL_PERI_IP_USER		2
+#define CLK_MOUT_PLL_PERI_UART_USER		3
+#define CLK_MOUT_PERI_SPI			4
+#define CLK_MOUT_PERI_USI00_USI			5
+
+#define CLK_DOUT_PERI_OTP			6
+
+#define CLK_DOUT_PERI_I2C_0			7
+#define CLK_DOUT_PERI_I2C_1			8
+#define CLK_DOUT_PERI_I2C_2			9
+#define CLK_DOUT_PERI_I2C_3			10
+#define CLK_DOUT_PERI_SPI			11
+#define CLK_DOUT_PERI_USI00_I2C			12
+#define CLK_DOUT_PERI_USI00_USI			13
+
+#define CLK_GOUT_PERI_BUSIF_TMU_PCLK		14
+#define CLK_GOUT_PERI_D_TZPC_PCLK		15
+#define CLK_GOUT_PERI_GPIO_PCLK			16
+#define CLK_GOUT_PERI_I2C_0_IPCLK		17
+#define CLK_GOUT_PERI_I2C_0_PCLK		18
+#define CLK_GOUT_PERI_I2C_1_IPCLK		19
+#define CLK_GOUT_PERI_I2C_1_PCLK		20
+#define CLK_GOUT_PERI_I2C_2_IPCLK		21
+#define CLK_GOUT_PERI_I2C_2_PCLK		22
+#define CLK_GOUT_PERI_I2C_3_IPCLK		23
+#define CLK_GOUT_PERI_I2C_3_PCLK		24
+#define CLK_GOUT_PERI_MCT_PCLK			25
+#define CLK_GOUT_PERI_OTP_OSCCLK		26
+#define CLK_GOUT_PERI_OTP_PCLK			27
+#define CLK_GOUT_PERI_CMU_PCLK			28
+#define CLK_GOUT_PERI_PWM_MOTOR_PCLK		29
+#define CLK_GOUT_PERI_BUS_CLK			30
+#define CLK_GOUT_PERI_I2C_0_CLK			31
+#define CLK_GOUT_PERI_I2C_1_CLK			32
+#define CLK_GOUT_PERI_I2C_2_CLK			33
+#define CLK_GOUT_PERI_I2C_3_CLK			34
+#define CLK_GOUT_PERI_OSCCLK			35
+#define CLK_GOUT_PERI_SPI_CLK			36
+#define CLK_GOUT_PERI_UART_CLK			37
+#define CLK_GOUT_PERI_USI00_I2C_CLK		38
+#define CLK_GOUT_PERI_USI00_USI_CLK		39
+#define CLK_GOUT_PERI_SLH_AXI_MI_P_CLK		40
+#define CLK_GOUT_PERI_SYSREG_PCLK		41
+#define CLK_GOUT_PERI_USI00_I2C_IPCLK		42
+#define CLK_GOUT_PERI_USI00_I2C_PCLK		43
+#define CLK_GOUT_PERI_USI00_USI_IPCLK		44
+#define CLK_GOUT_PERI_USI00_USI_PCLK		45
+#define CLK_GOUT_PERI_USI_SPI_IPCLK		46
+#define CLK_GOUT_PERI_USI_SPI_PCLK		47
+#define CLK_GOUT_PERI_USI_UART_IPCLK		48
+#define CLK_GOUT_PERI_USI_UART_PCLK		49
+#define CLK_GOUT_PERI_WDT0_PCLK			50
+#define CLK_GOUT_PERI_WDT1_PCLK			51
+#define CLK_GOUT_PERI_I2C_0			52
+#define CLK_GOUT_PERI_I2C_1			53
+#define CLK_GOUT_PERI_I2C_2			54
+#define CLK_GOUT_PERI_I2C_3			55
+#define CLK_GOUT_PERI_USI00_I2C			56
+
+/* CMU_FSYS */
+#define CLK_MOUT_PLL_FSYS_BUS_USER		1
+#define CLK_MOUT_PLL_FSYS_MMC_CARD_USER		2
+#define CLK_MOUT_PLL_FSYS_MMC_EMBD_USER		3
+#define CLK_MOUT_PLL_FSYS_USB20DRD_USER		4
+
+#define CLK_GOUT_FSYS_CMU_PCLK			5
+#define CLK_GOUT_FSYS_MMC_CARD_SDCLKIN		6
+#define CLK_GOUT_FSYS_MMC_EMBD_SDCLKIN		7
+#define CLK_GOUT_FSYS_OSCCLK			8
+#define CLK_GOUT_FSYS_USB20DRD_REFCLK		9
+#define CLK_GOUT_FSYS_USB20DRD_PHY_REFCLK	10
+#define CLK_GOUT_FSYS_D_TZPC_PCLK		11
+#define CLK_GOUT_FSYS_GPIO_PCLK			12
+#define CLK_GOUT_FSYS_MMC_CARD_ACLK		13
+#define CLK_GOUT_FSYS_MMC_EMBD_ACLK		14
+#define CLK_GOUT_FSYS_PPMU_ACLK			15
+#define CLK_GOUT_FSYS_PPMU_PCLK			16
+#define CLK_GOUT_FSYS_BUS_CLK			17
+#define CLK_GOUT_FSYS_SLH_AXI_MI_P_CLK		18
+#define CLK_GOUT_FSYS_SLH_AXI_SI_D_CLK		19
+#define CLK_GOUT_FSYS_SYSREG_PCLK		20
+#define CLK_GOUT_FSYS_USB20DRD_ACLK_PHYCTRL	21
+#define CLK_GOUT_FSYS_USB20DRD_BUS_CLK_EARLY	22
+#define CLK_GOUT_FSYS_US_64TO128_ACLK		23
+#define CLK_GOUT_FSYS_XIU_D_ACLK		24
+#define CLK_GOUT_FSYS_XIU_P_ACLK		25
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS5515_H */
diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
new file mode 100644
index 000000000000..a63283d5df5c
--- /dev/null
+++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) Stefan Dösinger.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_ZX297520V3_H
+#define __DT_BINDINGS_CLOCK_ZX297520V3_H
+
+#define ZX297520V3_M0_WCLK			0
+#define ZX297520V3_SRAM1_PCLK			1
+#define ZX297520V3_SRAM2_PCLK			2
+#define ZX297520V3_UART0_WCLK			3
+#define ZX297520V3_UART0_PCLK			4
+#define ZX297520V3_I2C0_WCLK			5
+#define ZX297520V3_I2C0_PCLK			6
+#define ZX297520V3_RTC_WCLK			7
+#define ZX297520V3_RTC_PCLK			8
+#define ZX297520V3_LPM_GSM_WCLK			9
+#define ZX297520V3_LPM_GSM_PCLK			10
+#define ZX297520V3_LPM_LTE_WCLK			11
+#define ZX297520V3_LPM_LTE_PCLK			12
+#define ZX297520V3_LPM_TD_WCLK			13
+#define ZX297520V3_LPM_TD_PCLK			14
+#define ZX297520V3_LPM_W_WCLK			15
+#define ZX297520V3_LPM_W_PCLK			16
+#define ZX297520V3_TIMER_T08_WCLK		17
+#define ZX297520V3_TIMER_T08_PCLK		18
+#define ZX297520V3_TIMER_T09_WCLK		19
+#define ZX297520V3_TIMER_T09_PCLK		20
+#define ZX297520V3_MPLL				21
+#define ZX297520V3_MPLL_D5			22
+#define ZX297520V3_DPLL				23
+#define ZX297520V3_GPLL				24
+#define ZX297520V3_GPLL_D2			25
+#define ZX297520V3_GATED_OSC26M			26
+#define ZX297520V3_PMM_WCLK			27
+#define ZX297520V3_PMM_PCLK			28
+#define ZX297520V3_OUT0_WCLK			29
+#define ZX297520V3_OUT1_WCLK			30
+#define ZX297520V3_OUT2_WCLK			31
+#define ZX297520V3_OUT32K_WCLK			32
+#define ZX297520V3_RMIIPHY_WCLK			33
+#define ZX297520V3_TIMER_T12_WCLK		34
+#define ZX297520V3_TIMER_T12_PCLK		35
+#define ZX297520V3_TIMER_T13_WCLK		36
+#define ZX297520V3_TIMER_T13_PCLK		37
+#define ZX297520V3_TIMER_T14_WCLK		38
+#define ZX297520V3_TIMER_T14_PCLK		39
+#define ZX297520V3_TIMER_T15_WCLK		40
+#define ZX297520V3_TIMER_T15_PCLK		41
+#define ZX297520V3_TIMER_T16_WCLK		42
+#define ZX297520V3_TIMER_T16_PCLK		43
+#define ZX297520V3_TIMER_T17_WCLK		44
+#define ZX297520V3_TIMER_T17_PCLK		45
+#define ZX297520V3_WDT_T18_WCLK			46
+#define ZX297520V3_WDT_T18_PCLK			47
+#define ZX297520V3_USIM1_WCLK			48
+#define ZX297520V3_USIM1_PCLK			49
+#define ZX297520V3_AHB_WCLK			50
+#define ZX297520V3_AHB_PCLK			51
+#define ZX297520V3_USB_WCLK			52
+#define ZX297520V3_USB_PCLK			53
+#define ZX297520V3_HSIC_WCLK			54
+#define ZX297520V3_HSIC_PCLK			55
+#define ZX297520V3_GSM_32K			56
+#define ZX297520V3_GSM_26M			57
+#define ZX297520V3_GSM_48M			58
+#define ZX297520V3_GSM_104M			59
+#define ZX297520V3_GSM_156M			60
+#define ZX297520V3_ABB_WCLK			61
+
+#define ZX297520V3_SYS_TIMER_WCLK		0
+#define ZX297520V3_CPU_WCLK			1
+#define ZX297520V3_CPU_PCLK			2
+#define ZX297520V3_ZSP_WCLK			3
+#define ZX297520V3_ZSP_PCLK			4
+#define ZX297520V3_DDR_CTRL_PCLK		5
+#define ZX297520V3_DDR_CTRL_WCLK		6
+#define ZX297520V3_EDCP_WCLK			7
+#define ZX297520V3_EDCP_PCLK			8
+#define ZX297520V3_SD0_WCLK			9
+#define ZX297520V3_SD0_PCLK			10
+#define ZX297520V3_SD0_CDET			11
+#define ZX297520V3_SD1_WCLK			12
+#define ZX297520V3_SD1_PCLK			13
+#define ZX297520V3_SD1_CDET			14
+#define ZX297520V3_NAND_WCLK			15
+#define ZX297520V3_NAND_PCLK			16
+#define ZX297520V3_DMA_PCLK			17
+#define ZX297520V3_MBOX_PCLK			18
+#define ZX297520V3_PDCFG_WCLK			19
+#define ZX297520V3_PDCFG_PCLK			20
+#define ZX297520V3_RFFE_WCLK			21
+#define ZX297520V3_SSC_WCLK			22
+#define ZX297520V3_SSC_PCLK			23
+#define ZX297520V3_AXI_WCLK			24
+#define ZX297520V3_GMAC_WCLK			25
+#define ZX297520V3_GMAC_PCLK			26
+#define ZX297520V3_GMAC_AHB			27
+#define ZX297520V3_VOU_WCLK			28
+#define ZX297520V3_VOU_PCLK			29
+#define ZX297520V3_LSP_MPLL_D5_WCLK		30
+#define ZX297520V3_LSP_MPLL_D4_WCLK		31
+#define ZX297520V3_LSP_MPLL_D6_WCLK		32
+#define ZX297520V3_LSP_MPLL_D8_WCLK		33
+#define ZX297520V3_LSP_MPLL_D12_WCLK		34
+#define ZX297520V3_LSP_OSC26M_WCLK		35
+#define ZX297520V3_LSP_OSC32K_WCLK		36
+#define ZX297520V3_LSP_PCLK			37
+#define ZX297520V3_LSP_TDM_WCLK			38
+#define ZX297520V3_LSP_DPLL_D4_WCLK		39
+#define ZX297520V3_SRAM0_PCLK			40
+#define ZX297520V3_GSM_CFG_PCLK			41
+#define ZX297520V3_LTE_MODEM_WCLK		42
+#define ZX297520V3_LTE_MODEM_PCLK		43
+
+#define ZX297520V3_TIMER_L1_WCLK		0
+#define ZX297520V3_TIMER_L1_PCLK		1
+#define ZX297520V3_WDT_L2_WCLK			2
+#define ZX297520V3_WDT_L2_PCLK			3
+#define ZX297520V3_WDT_L3_WCLK			4
+#define ZX297520V3_WDT_L3_PCLK			5
+#define ZX297520V3_PWM_WCLK			6
+#define ZX297520V3_PWM_PCLK			7
+#define ZX297520V3_I2S0_WCLK			8
+#define ZX297520V3_I2S0_PCLK			9
+#define ZX297520V3_I2S1_WCLK			10
+#define ZX297520V3_I2S1_PCLK			11
+#define ZX297520V3_QSPI_WCLK			12
+#define ZX297520V3_QSPI_PCLK			13
+#define ZX297520V3_UART1_WCLK			14
+#define ZX297520V3_UART1_PCLK			15
+#define ZX297520V3_I2C1_WCLK			16
+#define ZX297520V3_I2C1_PCLK			17
+#define ZX297520V3_SPI0_WCLK			18
+#define ZX297520V3_SPI0_PCLK			19
+#define ZX297520V3_TIMER_LB_WCLK		20
+#define ZX297520V3_TIMER_LB_PCLK		21
+#define ZX297520V3_TIMER_LC_WCLK		22
+#define ZX297520V3_TIMER_LC_PCLK		23
+#define ZX297520V3_UART2_WCLK			24
+#define ZX297520V3_UART2_PCLK			25
+#define ZX297520V3_WDT_LE_WCLK			26
+#define ZX297520V3_WDT_LE_PCLK			27
+#define ZX297520V3_TIMER_LF_WCLK		28
+#define ZX297520V3_TIMER_LF_PCLK		29
+#define ZX297520V3_SPI1_WCLK			30
+#define ZX297520V3_SPI1_PCLK			31
+#define ZX297520V3_TIMER_L11_WCLK		32
+#define ZX297520V3_TIMER_L11_PCLK		33
+#define ZX297520V3_TDM_WCLK			34
+#define ZX297520V3_TDM_PCLK			35
+
+#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
diff --git a/include/dt-bindings/phy/zte,zx297520v3-topcrm.h b/include/dt-bindings/phy/zte,zx297520v3-topcrm.h
new file mode 100644
index 000000000000..b36ccf2f54ef
--- /dev/null
+++ b/include/dt-bindings/phy/zte,zx297520v3-topcrm.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) Stefan Dösinger.
+ */
+
+#ifndef __DT_BINDINGS_PHY_ZTE_ZX297520V3_TOPCRM_H
+#define __DT_BINDINGS_PHY_ZTE_ZX297520V3_TOPCRM_H
+
+#define ZX297520V3_USB_PHY	0
+#define ZX297520V3_HSIC_PHY	1
+
+#endif /* __DT_BINDINGS_PHY_ZTE_ZX297520V3_TOPCRM_H */
diff --git a/include/dt-bindings/reset/anlogic,dr1v90-cru.h b/include/dt-bindings/reset/anlogic,dr1v90-cru.h
new file mode 100644
index 000000000000..c5b7aae1ab6a
--- /dev/null
+++ b/include/dt-bindings/reset/anlogic,dr1v90-cru.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ANLOGIC_DR1V90_CRU_H_
+#define _DT_BINDINGS_RESET_ANLOGIC_DR1V90_CRU_H_
+
+#define RESET_OCM		0
+#define RESET_QSPI		1
+#define RESET_SMC		2
+#define RESET_WDT		3
+#define RESET_DMAC_AXI		4
+#define RESET_DMAC_AHB		5
+#define RESET_NPU		6
+#define RESET_JPU		7
+#define RESET_DDRBUS		8
+#define RESET_NIC_HP0		9
+#define RESET_NIC_HP1		10
+#define RESET_NIC_GP0M		11
+#define RESET_NIC_GP1M		12
+#define RESET_GPIO		13
+#define RESET_IPC		14
+#define RESET_USB0		15
+#define RESET_USB1		16
+#define RESET_GBE0		17
+#define RESET_GBE1		18
+#define RESET_SDIO0		19
+#define RESET_SDIO1		20
+#define RESET_UART0		21
+#define RESET_UART1		22
+#define RESET_SPI0		23
+#define RESET_SPI1		24
+#define RESET_CAN0		25
+#define RESET_CAN1		26
+#define RESET_TTC0		27
+#define RESET_TTC1		28
+#define RESET_I2C0		29
+#define RESET_I2C1		30
+
+#endif /* _DT_BINDINGS_RESET_ANLOGIC_DR1V90_CRU_H_ */
diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h
new file mode 100644
index 000000000000..b21d5901a7b9
--- /dev/null
+++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) Stefan Dösinger.
+ */
+
+#ifndef __DT_BINDINGS_RESET_ZX297520V3_H
+#define __DT_BINDINGS_RESET_ZX297520V3_H
+
+#define ZX297520V3_ZSP_CORE_RESET		0
+#define ZX297520V3_UART0_RESET			1
+#define ZX297520V3_I2C0_RESET			2
+#define ZX297520V3_RTC_RESET			3
+#define ZX297520V3_TIMER_T08_RESET		4
+#define ZX297520V3_TIMER_T09_RESET		5
+#define ZX297520V3_PMM_RESET			6
+#define ZX297520V3_GPIO_RESET			7
+#define ZX297520V3_GPIO8_RESET			8
+#define ZX297520V3_TIMER_T12_RESET		9
+#define ZX297520V3_TIMER_T13_RESET		10
+#define ZX297520V3_TIMER_T14_RESET		11
+#define ZX297520V3_TIMER_T15_RESET		12
+#define ZX297520V3_TIMER_T16_RESET		13
+#define ZX297520V3_TIMER_T17_RESET		14
+#define ZX297520V3_WDT_T18_RESET		15
+#define ZX297520V3_USIM1_RESET			16
+#define ZX297520V3_AHB_RESET			17
+#define ZX297520V3_USB_RESET			18
+#define ZX297520V3_HSIC_RESET			19
+
+#define ZX297520V3_CPU_RESET			0
+#define ZX297520V3_ZSP_BUS_RESET		1
+#define ZX297520V3_DDR_CTRL_RESET		2
+#define ZX297520V3_EDCP_RESET			3
+#define ZX297520V3_SD0_RESET			4
+#define ZX297520V3_SD1_RESET			5
+#define ZX297520V3_NAND_RESET			6
+#define ZX297520V3_PDCFG_RESET			7
+#define ZX297520V3_SSC_RESET			8
+#define ZX297520V3_GMAC_RESET			9
+#define ZX297520V3_VOU_RESET			10
+#define ZX297520V3_LSP_RESET			11
+
+#define ZX297520V3_TIMER_L1_RESET		0
+#define ZX297520V3_WDT_L2_RESET			1
+#define ZX297520V3_WDT_L3_RESET			2
+#define ZX297520V3_PWM_RESET			3
+#define ZX297520V3_I2S0_RESET			4
+#define ZX297520V3_I2S1_RESET			5
+#define ZX297520V3_QSPI_RESET			6
+#define ZX297520V3_UART1_RESET			7
+#define ZX297520V3_I2C1_RESET			8
+#define ZX297520V3_SPI0_RESET			9
+#define ZX297520V3_TIMER_LB_RESET		10
+#define ZX297520V3_TIMER_LC_RESET		11
+#define ZX297520V3_UART2_RESET			12
+#define ZX297520V3_WDT_LE_RESET			13
+#define ZX297520V3_TIMER_LF_RESET		14
+#define ZX297520V3_SPI1_RESET			15
+#define ZX297520V3_TIMER_L11_RESET		16
+#define ZX297520V3_TDM_RESET			17
+
+#endif /* __DT_BINDINGS_RESET_ZX297520V3_H */
diff --git a/include/dt-bindings/soc/airoha,scu-ssr.h b/include/dt-bindings/soc/airoha,scu-ssr.h
new file mode 100644
index 000000000000..33c64844ada3
--- /dev/null
+++ b/include/dt-bindings/soc/airoha,scu-ssr.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef __DT_BINDINGS_AIROHA_SCU_SSR_H
+#define __DT_BINDINGS_AIROHA_SCU_SSR_H
+
+#define AIROHA_SCU_SERDES_PCIE1		0
+#define AIROHA_SCU_SERDES_PCIE2		1
+#define AIROHA_SCU_SERDES_USB1		2
+#define AIROHA_SCU_SERDES_USB2		3
+
+#endif /* __DT_BINDINGS_AIROHA_SCU_SSR_H */
diff --git a/include/kunit/clk.h b/include/kunit/clk.h
index f226044cc78d..0b5ab8e971c9 100644
--- a/include/kunit/clk.h
+++ b/include/kunit/clk.h
@@ -29,5 +29,7 @@ int of_clk_hw_register_kunit(struct kunit *test, struct device_node *node,
 int of_clk_add_hw_provider_kunit(struct kunit *test, struct device_node *np,
 				 struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data),
 				 void *data);
+struct device_node *clk_of_find_node_by_name_kunit(struct kunit *test, struct device_node *from,
+						   const char *name);
 
 #endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index dc8e161f9c2c..a355d1ee5189 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -7,6 +7,7 @@
 #define __LINUX_CLK_PROVIDER_H
 
 #include <dt-bindings/clock/clock.h>
+#include <linux/bits.h>
 #include <linux/of.h>
 #include <linux/of_clk.h>
 
@@ -50,6 +51,7 @@ struct clk;
 struct clk_hw;
 struct clk_core;
 struct dentry;
+struct module;
 
 /**
  * struct clk_rate_request - Structure encoding the clk constraints that
@@ -351,8 +353,9 @@ struct clk_init_data {
  * @core: pointer to the struct clk_core instance that points back to this
  * struct clk_hw instance
  *
- * @clk: pointer to the per-user struct clk instance that can be used to call
- * into the clk API
+ * @clk: pointer to the per-user struct clk instance. This will be removed at
+ * some point in the future, Please consider the field obsolete and do not use
+ * it. Use clk_hw_get_clk() to get a per-user struct clk from a struct clk_hw.
  *
  * @init: pointer to struct clk_init_data that contains the init data shared
  * with the common clock framework. This pointer will be set to NULL once
@@ -755,7 +758,7 @@ struct clk_divider {
 	spinlock_t	*lock;
 };
 
-#define clk_div_mask(width)	((1 << (width)) - 1)
+#define clk_div_mask(width)	GENMASK((width) - 1, 0)
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 #define CLK_DIVIDER_ONE_BASED		BIT(0)
@@ -1474,10 +1477,24 @@ static inline struct clk_hw *__clk_get_hw(struct clk *clk)
 }
 #endif
 
-struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
+struct clk *__clk_hw_get_clk(struct clk_hw *hw, const char *con_id,
+			     struct module *owner);
 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
 				const char *con_id);
 
+/**
+ * clk_hw_get_clk - get clk consumer given a clk_hw
+ * @hw: clk_hw associated with the clk being consumed
+ * @con_id: connection ID string on device
+ *
+ * Return: new clk consumer
+ * This is the function to be used by providers which need
+ * to get a consumer clk and act on the clock element
+ * Calls to this function must be balanced with calls to clk_put()
+ */
+#define clk_hw_get_clk(hw, con_id) \
+	__clk_hw_get_clk((hw), (con_id), THIS_MODULE)
+
 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 3650e926e93f..f1034e14c1a4 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -170,7 +170,7 @@ struct tegra210_clk_emc_provider {
 	struct module *owner;
 	struct device *dev;
 
-	struct tegra210_clk_emc_config *configs;
+	struct tegra210_clk_emc_config *configs __counted_by_ptr(num_configs);
 	unsigned int num_configs;
 
 	int (*set_rate)(struct device *dev,
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 54a3fa370004..61c4abf19995 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -51,7 +51,7 @@ struct clk_omap_reg {
  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
  * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
- * @dcc_rate: rate atleast which DCC @dcc_mask must be set
+ * @dcc_rate: rate at least which DCC @dcc_mask must be set
  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
  * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
diff --git a/include/linux/device/driver.h b/include/linux/device/driver.h
index 768a1334c0a1..29fbc01ef06f 100644
--- a/include/linux/device/driver.h
+++ b/include/linux/device/driver.h
@@ -297,4 +297,35 @@ static int __init __driver##_init(void) \
 } \
 device_initcall(__driver##_init);
 
+/**
+ * subsys_driver() - Helper macro for drivers that don't do anything special
+ * in init/exit but have to register earlier, at subsys_initcall level, when
+ * built in. This eliminates a lot of boilerplate. Each driver may only use
+ * this macro once, and calling it replaces the init/exit boilerplate.
+ *
+ * @__driver: driver name
+ * @__register: register function for this driver type
+ * @__unregister: unregister function for this driver type
+ * @...: Additional arguments to be passed to __register and __unregister.
+ *
+ * This is meant to be a direct parallel of module_driver() above, but with
+ * the init call promoted to subsys_initcall() for built-in drivers so they
+ * are available earlier during boot. When built as a module subsys_initcall()
+ * collapses to module_init() and the normal module init/exit paths are used.
+ *
+ * Use this macro to construct bus specific macros for registering drivers,
+ * and do not use it on its own.
+ */
+#define subsys_driver(__driver, __register, __unregister, ...) \
+static int __init __driver##_init(void) \
+{ \
+	return __register(&(__driver), ##__VA_ARGS__); \
+} \
+subsys_initcall(__driver##_init) \
+static void __exit __driver##_exit(void) \
+{ \
+	__unregister(&(__driver), ##__VA_ARGS__); \
+} \
+module_exit(__driver##_exit)
+
 #endif	/* _DEVICE_DRIVER_H_ */
diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h
index 3d5bbcbae730..3bd0f1f0d870 100644
--- a/include/linux/platform_device.h
+++ b/include/linux/platform_device.h
@@ -344,6 +344,19 @@ static inline void platform_set_drvdata(struct platform_device *pdev,
 #define builtin_platform_driver(__platform_driver) \
 	builtin_driver(__platform_driver, platform_driver_register)
 
+/*
+ * subsys_platform_driver() - Helper macro for drivers that don't do anything
+ * special in module init/exit but need to register earlier, at
+ * subsys_initcall level, when built in.  This eliminates a lot of
+ * boilerplate.  Each driver may only use this macro once, and calling it
+ * replaces module_init() and module_exit().  This is meant to be a parallel
+ * of module_platform_driver() above, but with the init call promoted to
+ * subsys_initcall() so built-in providers are available earlier during boot.
+ */
+#define subsys_platform_driver(__platform_driver) \
+	subsys_driver(__platform_driver, platform_driver_register, \
+			platform_driver_unregister)
+
 /* module_platform_driver_probe() - Helper macro for drivers that don't do
  * anything special in module init/exit.  This eliminates a lot of
  * boilerplate.  Each module may only use this macro once, and
@@ -376,6 +389,23 @@ static int __init __platform_driver##_init(void) \
 } \
 device_initcall(__platform_driver##_init); \
 
+/*
+ * subsys_platform_driver_probe() - Helper macro for drivers that don't do
+ * anything special in device init and have no exit, but need to register
+ * earlier, at subsys_initcall level.  This eliminates some boilerplate.  Each
+ * driver may only use this macro once, and using it replaces subsys_initcall.
+ * This is meant to be a parallel of builtin_platform_driver_probe above, but
+ * with the init call promoted to subsys_initcall so the provider is available
+ * earlier during boot.
+ */
+#define subsys_platform_driver_probe(__platform_driver, __platform_probe) \
+static int __init __platform_driver##_init(void) \
+{ \
+	return platform_driver_probe(&(__platform_driver), \
+				     __platform_probe);    \
+} \
+subsys_initcall(__platform_driver##_init) \
+
 #define platform_create_bundle(driver, probe, res, n_res, data, size) \
 	__platform_create_bundle(driver, probe, res, n_res, data, size, THIS_MODULE, KBUILD_MODNAME)
 extern struct platform_device *__platform_create_bundle(