diff options
| author | Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> | 2026-09-01 11:53:21 +0800 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-10-13 09:49:39 -0500 |
| commit | bc07c3a51168a38a79c171983cc6af90535cb1eb (patch) | |
| tree | 63898351c19523e648153942bf13f8493471cec9 /include | |
| parent | cbe415e116ed1cd9ad2a115683688b797cafb14a (diff) | |
dt-bindings: clock: qcom: nord-negcc: Add the secondary QUSB2 PHY reset
The NE_GCC block has two eUSB2 PHY block resets - PRIM and SEC - but
right now only the primary is registered. Add the secondary, which is
required by the usb_1 eUSB2 PHY.
Note that the SoC has three eUSB2 PHYs but only these two QUSB2PHY
resets: the HS-only USB20 tile has no dedicated QUSB2PHY reset and
is instead reset as a whole via NE_GCC_USB20_PRIM_BCR.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://patch.msgid.link/20260901035322.654-2-shengchao.guo@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/qcom,nord-negcc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindings/clock/qcom,nord-negcc.h index a7024317e90b..ad9ff389956d 100644 --- a/include/dt-bindings/clock/qcom,nord-negcc.h +++ b/include/dt-bindings/clock/qcom,nord-negcc.h @@ -121,5 +121,6 @@ #define NE_GCC_USB3PHY_PHY_PRIM_BCR 11 #define NE_GCC_USB3PHY_PHY_SEC_BCR 12 #define NE_GCC_QUSB2PHY_PRIM_BCR 13 +#define NE_GCC_QUSB2PHY_SEC_BCR 14 #endif |