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authorJakub Kicinski <kuba@kernel.org>2025-06-13 18:21:59 -0700
committerJakub Kicinski <kuba@kernel.org>2025-06-13 18:21:59 -0700
commitd4d4126fc5d23e45e6eb3b47663f1df5a5f486b8 (patch)
tree3eeaae62ddaa48b1ac2b531fc4cc700b4388fa87 /include
parentbd1d76a6f18f2222dc08c5aa9ebcd0445111a27d (diff)
parent863c7e5059363a37dba19df78a37fb0960b331fa (diff)
Merge branch 'dpll-add-all-inputs-phase-offset-monitor'
Arkadiusz Kubalewski says: ==================== dpll: add all inputs phase offset monitor Add dpll device level feature: phase offset monitor. Phase offset measurement is typically performed against the current active source. However, some DPLL (Digital Phase-Locked Loop) devices may offer the capability to monitor phase offsets across all available inputs. The attribute and current feature state shall be included in the response message of the ``DPLL_CMD_DEVICE_GET`` command for supported DPLL devices. In such cases, users can also control the feature using the ``DPLL_CMD_DEVICE_SET`` command by setting the ``enum dpll_feature_state`` values for the attribute. Once enabled the phase offset measurements for the input shall be returned in the ``DPLL_A_PIN_PHASE_OFFSET`` attribute. Implement feature support in ice driver for dpll-enabled devices. Verify capability: $ ./tools/net/ynl/pyynl/cli.py \ --spec Documentation/netlink/specs/dpll.yaml \ --dump device-get [{'clock-id': 4658613174691613800, 'id': 0, 'lock-status': 'locked-ho-acq', 'mode': 'automatic', 'mode-supported': ['automatic'], 'module-name': 'ice', 'type': 'eec'}, {'clock-id': 4658613174691613800, 'id': 1, 'lock-status': 'locked-ho-acq', 'mode': 'automatic', 'mode-supported': ['automatic'], 'module-name': 'ice', 'phase-offset-monitor': 'disable', 'type': 'pps'}] Enable the feature: $ ./tools/net/ynl/pyynl/cli.py \ --spec Documentation/netlink/specs/dpll.yaml \ --do device-set --json '{"id":1, "phase-offset-monitor":"enable"}' Verify feature is enabled: $ ./tools/net/ynl/pyynl/cli.py \ --spec Documentation/netlink/specs/dpll.yaml \ --dump device-get [ [...] {'capabilities': {'all-inputs-phase-offset-monitor'}, 'clock-id': 4658613174691613800, 'id': 1, [...] 'phase-offset-monitor': 'enable', [...]] v6: - rebase. ==================== Link: https://patch.msgid.link/20250612152835.1703397-1-arkadiusz.kubalewski@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'include')
-rw-r--r--include/linux/dpll.h8
-rw-r--r--include/uapi/linux/dpll.h12
2 files changed, 20 insertions, 0 deletions
diff --git a/include/linux/dpll.h b/include/linux/dpll.h
index 5e4f9ab1cf75..6ad6c2968a28 100644
--- a/include/linux/dpll.h
+++ b/include/linux/dpll.h
@@ -30,6 +30,14 @@ struct dpll_device_ops {
void *dpll_priv,
unsigned long *qls,
struct netlink_ext_ack *extack);
+ int (*phase_offset_monitor_set)(const struct dpll_device *dpll,
+ void *dpll_priv,
+ enum dpll_feature_state state,
+ struct netlink_ext_ack *extack);
+ int (*phase_offset_monitor_get)(const struct dpll_device *dpll,
+ void *dpll_priv,
+ enum dpll_feature_state *state,
+ struct netlink_ext_ack *extack);
};
struct dpll_pin_ops {
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index bf97d4b6d51f..349e1b3ca1ae 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -192,6 +192,17 @@ enum dpll_pin_capabilities {
#define DPLL_PHASE_OFFSET_DIVIDER 1000
+/**
+ * enum dpll_feature_state - Allow control (enable/disable) and status checking
+ * over features.
+ * @DPLL_FEATURE_STATE_DISABLE: feature shall be disabled
+ * @DPLL_FEATURE_STATE_ENABLE: feature shall be enabled
+ */
+enum dpll_feature_state {
+ DPLL_FEATURE_STATE_DISABLE,
+ DPLL_FEATURE_STATE_ENABLE,
+};
+
enum dpll_a {
DPLL_A_ID = 1,
DPLL_A_MODULE_NAME,
@@ -204,6 +215,7 @@ enum dpll_a {
DPLL_A_TYPE,
DPLL_A_LOCK_STATUS_ERROR,
DPLL_A_CLOCK_QUALITY_LEVEL,
+ DPLL_A_PHASE_OFFSET_MONITOR,
__DPLL_A_MAX,
DPLL_A_MAX = (__DPLL_A_MAX - 1)