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authorVignesh Raghavendra <vigneshr@ti.com>2021-05-10 23:36:01 +0530
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-06-10 13:39:21 +0200
commitd866a6e61a4de0eb13973eb8a85c780323876711 (patch)
treeeb33c8a607fca9db366fc84ee75705d7e92a2289 /include
parenta1bf16616d8351a2e79400d6d19608befb2ce1dd (diff)
arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent
[ Upstream commit 52ae30f55a2a40cff549fac95de82f25403bd387 ] Traffic through main NAVSS interconnect is coherent wrt ARM caches on J7200 SoC. Add missing dma-coherent property to main_navss node. Also add dma-ranges to be consistent with mcu_navss node and with AM65/J721e main_navss and mcu_navss nodes. Fixes: d361ed88455fe ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210510180601.19458-1-vigneshr@ti.com Signed-off-by: Sasha Levin <sashal@kernel.org>
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