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| author | Dave Airlie <airlied@redhat.com> | 2017-02-08 11:34:56 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2017-02-08 11:34:56 +1000 |
| commit | f864b00e03a0308beae7c88e2e145a429d5872dd (patch) | |
| tree | 0b92a75bcab2e841871499562897b688afa55a70 /include | |
| parent | 4eaa39c63caf535dc1a8cc43b9a8677a100c09e1 (diff) | |
| parent | 7ff093d09f8f027c317282e18b566473df53e8a1 (diff) | |
Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
Summary:
- Add UHD support on TM2/TM2E boards.
. adding interlace mode support and 297MHz pixel clock support
for UHD mode, setting sysreg register in case of HW trigger mode,
and adding SiI8620 MHL bridge device support.
- Fix trigger mode issue on Rinato board.
. On Rinato board, HW trigger mode doesn't work so fix it.
- Some fixup and cleanup.
* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos:
drm/exynos: fimd: Do not use HW trigger for exynos3250
drm/exynos/hdmi: add bridge support
drm/exynos/decon5433: signal vblank only on odd fields
drm/exynos/decon5433: add support for interlace modes
drm/exynos/hdmi: fix PLL for 27MHz settings
drm/exynos/hdmi: fix VSI infoframe registers
drm/exynos/hdmi: add 297MHz pixel clock support
drm/exynos: g2d: change platform driver name to 'exynos-drm-g2d'
drm/exynos/decon5433: configure sysreg in case of hardware trigger
Diffstat (limited to 'include')
| -rw-r--r-- | include/video/exynos5433_decon.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h index 0098a522d9f4..ef8e2a8ad0af 100644 --- a/include/video/exynos5433_decon.h +++ b/include/video/exynos5433_decon.h @@ -89,6 +89,8 @@ #define VIDCON0_ENVID_F (1 << 0) /* VIDOUTCON0 */ +#define VIDOUT_INTERLACE_FIELD_F (1 << 29) +#define VIDOUT_INTERLACE_EN_F (1 << 28) #define VIDOUT_LCD_ON (1 << 24) #define VIDOUT_IF_F_MASK (0x3 << 20) #define VIDOUT_RGB_IF (0x0 << 20) |