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| author | Peter Zijlstra <peterz@infradead.org> | 2026-05-19 12:18:01 +0200 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-05-19 12:18:01 +0200 |
| commit | a26d9208c1376ac3877d9f12e697f83368e2af1c (patch) | |
| tree | 1f68b9ae26b8b88a7d1f24fea2a6df87e4c0fee5 /init/Kconfig | |
| parent | dd29c017aed628076e915fe4cdfb5392fd4c5cab (diff) | |
| parent | c99b8593b060931c5a0a4b701689f8d6a2c00dbf (diff) | |
Merge branch 'sched/cache'
Merge the cache aware balancer topic branch.
# Conflicts:
# kernel/sched/topology.c
Diffstat (limited to 'init/Kconfig')
| -rw-r--r-- | init/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/init/Kconfig b/init/Kconfig index 2937c4d308ae..a52cd95ef171 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -1019,6 +1019,17 @@ config NUMA_BALANCING This system will be inactive on UMA systems. +config SCHED_CACHE + bool "Cache aware load balance" + default y + depends on SMP + help + When enabled, the scheduler will attempt to aggregate tasks from + the same process onto a single Last Level Cache (LLC) domain when + possible. This improves cache locality by keeping tasks that share + resources within the same cache domain, reducing cache misses and + lowering data access latency. + config NUMA_BALANCING_DEFAULT_ENABLED bool "Automatically enable NUMA aware memory/task placement" default y |