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| author | Timur Kristóf <timur.kristof@gmail.com> | 2026-05-13 22:04:13 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-05-19 12:10:45 -0400 |
| commit | 3e5a1d5bb2ff061e64c7992f8e5404dfd4c2d0f3 (patch) | |
| tree | 5054c850099f6e075b6291362d836a63c9af13ec /io_uring/alloc_cache.h | |
| parent | 3ebcab11320588fd9bb17a26027dddce4419ae43 (diff) | |
drm/amdgpu/vce1: Fix VCE 1 firmware size and offsets
The VCPU BO contains the actual FW at an offset, but
it was not calculated into the VCPU BO size.
Subtract this from the FW size to make sure there is
no out of bounds access.
Make sure the stack and data offsets are aligned to
the 32K TLB size.
Check that the FW microcode actually fits in the
space that is reserved for it.
Fixes: d4a640d4b9f3 ("drm/amdgpu/vce1: Implement VCE1 IP block (v2)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit c16fe59f622a080fc457a57b3e8f14c780699449)
Diffstat (limited to 'io_uring/alloc_cache.h')
0 files changed, 0 insertions, 0 deletions