diff options
| author | Guixiong Wei <weiguixiong@bytedance.com> | 2026-10-08 13:19:54 +0800 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2026-10-16 09:49:00 +0200 |
| commit | cf1f186e08dadb5abc4410d10fe3ada7ebf801ae (patch) | |
| tree | 7661d0ba5e3b73e76e96754dcb371d6dee560d32 /kernel/events | |
| parent | 24a19b953e2a3d0ea5a8c4951a0ab8f32720c907 (diff) | |
perf/x86/intel/uncore: Fix DMR CXL CM invert filter
The DMR CXL CM PMU places its invert filter at config bit 21 and its
9-bit threshold at bits 23-31. However, dmr_uncore_cxlcm uses
GENERIC_PMON_RAW_EVENT_MASK, which covers the threshold through the
generic bit 23 invert field and bits 24-31 threshold field, but does not
include the relocated invert bit. As a result, uncore_pmu_event_init()
silently clears bit 21 and inv=1 programs the same configuration as
inv=0.
Add bit 21 to a DMR CXL CM-specific event mask so the requested invert
filter reaches hardware.
Fixes: 6daf2c35b835 ("perf/x86/intel/uncore: Add IMH PMON support for Diamond Rapids")
Signed-off-by: Guixiong Wei <weiguixiong@bytedance.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Zide Chen <zide.chen@intel.com>
Link: https://patch.msgid.link/20261008051953.6293-2-weiguixiong@bytedance.com
Diffstat (limited to 'kernel/events')
0 files changed, 0 insertions, 0 deletions