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authorMiquel Raynal <miquel.raynal@bootlin.com>2019-11-17 18:34:01 +0100
committerMiquel Raynal <miquel.raynal@bootlin.com>2019-11-17 18:34:01 +0100
commit8389a7b909f252e74ea92b2794de8d660cfee96e (patch)
treea947f3080e953e4a44417389b3f2b69d4817be2e /kernel/panic.c
parentad39b5a1ed68032292794b41a5f9e41ea69f8052 (diff)
parent83cba933a6db1dd4d7ac85170f99461fbc339eff (diff)
Merge tag 'spi-nor/for-5.5' into mtd/next
SPI NOR core changes: - introduce 'struct spi_nor_controller_ops', - clean the Register Operations methods, - use dev_dbg insted of dev_err for low level info, - fix retlen handling in sst_write(), - fix silent truncations in spi_nor_read and spi_nor_read_raw(), - fix the clearing of QE bit on lock()/unlock(), - rework the disabling of the block write protection, - rework the Quad Enable methods, - make sure nor->spimem and nor->controller_ops are mutually exclusive, - set default Quad Enable method for ISSI flashes, - add support for few flashes. SPI NOR controller drivers changes: - intel-spi: - support chips without software sequencer, - add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
Diffstat (limited to 'kernel/panic.c')
-rw-r--r--kernel/panic.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/panic.c b/kernel/panic.c
index 47e8ebccc22b..f470a038b05b 100644
--- a/kernel/panic.c
+++ b/kernel/panic.c
@@ -180,6 +180,7 @@ void panic(const char *fmt, ...)
* after setting panic_cpu) from invoking panic() again.
*/
local_irq_disable();
+ preempt_disable_notrace();
/*
* It's possible to come here directly from a panic-assertion and