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| author | Yangyu Chen <cyy@cyyself.name> | 2026-02-04 01:21:48 +0800 |
|---|---|---|
| committer | Thomas Gleixner <tglx@kernel.org> | 2026-02-04 11:13:58 +0100 |
| commit | 889588d750506d86ba16ae3b968b5ffc5937d5f8 (patch) | |
| tree | af742c6085b43503f312650ee459aa6aaf6d936d /kernel | |
| parent | 42e025b719c128bdf8ff88584589a1e4a2448c81 (diff) | |
dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC
In PLIC, interrupt source 0 is reserved and should not be used.
Therefore, the valid interrupt sources are from 1 to riscv,ndev
inclusive.
Update the documentation to clarify this point.
[ tglx: Fixup subject prefix ]
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/tencent_720A4669773B1EE15EC720869C35C2F0490A@qq.com
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions