Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Here's the clk changes for the merge window which is dominated in the
  diffstat by Qualcomm churning out new SoCs that need clk drivers.

  Looking beyond the sheer amount of lines of mostly data there we have
  a clk nexus DT binding change in the core clk framework and a driver
  core patch to add a subsys driver macro.

  The clock nexus support is useful for devices that map clks internally
  or for connectors on a board that route clock signals to another
  board. I suspect the use of this will expand in the future, so we have
  unit tests to make sure it doesn't break.

  The driver core change adds subsys_driver() and
  subsys_platform_driver() so we can register early drivers without
  open-coding that all (module_platform_driver() is at device initcall
  level so it isn't be used).

  Beyond the core framework bits we have lots of changes all over the
  tree to initialize 'struct clk_init_data'. The potential risk here is
  that someone forgets to initialize all the members of that structure
  and either the clk flags cause weird behavior later on or the parents
  are pointing at junk and the clk is orphaned forever. The patches just
  initialize the thing with zeroes to be safe. Longer term we should
  probably move this struct out of 'struct clk_hw' and pass it during
  clk registration time. That's a much bigger change and would require
  restructuring entire drivers that rely on the pointer being there.

  Finally, we have the usual fixes like calculation updates for
  dividers, handling error paths during clk registration, or fixing clk
  data now that drivers are using them. Those patches are dwarfed by the
  amount of new SoC support and only affect those SoCs and the consumers
  of those clks. Overall I'm more concerned the clk_init_data patches
  are going to expose some latent bugs that we didn't notice before
  because something was relying on clks being orphaned and now they're
  not.

  Core:
   - subsys_driver() / subsys_platform_driver() macros
   - Clock nexus DT binding support (with KUnit tests)
   - Spread-spectrum configuration validation
   - Fully initialize struct clk_init_data across many drivers

  New Drivers:
   - Anlogic DR1V90 CRU
   - ZTE zx297520v3 top, matrix, and LSP clocks
   - Samsung Exynos5515 and ACPM driver extended to Exynos850.
   - Qualcomm Eliza camera, camera-BIST, GPU, and video clks
   - Qualcomm Hawi / Maili camera and GPU controllers
   - Qualcomm Kuno global, RPMh
   - Qualcomm MSM8952 global, RPM
   - Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets
   - Qualcomm IPQ5210 / IPQ9650 network clocks
   - i.MX93 350 MHz fractional-N GP-PLL for display
   - i.MX pll14xx spread-spectrum clock generation
   - Amlogic A9 SCMI clock controller
   - Allwinner single-divider "update bit" support
   - EN7523 Serdes port selection"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (316 commits)
  clk: imx: pll14xx: support spread spectrum clock generation
  clk: cdce925: Size the PLL child name buffer for any int
  clk: stm32: fix clock array size for STM32MP21
  dt-bindings: clock: Convert HiSilicon clocks to DT schema
  clk: lmk04832: Handle reset GPIO lookup errors
  dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
  clk: tegra: bpmp: remove kcalloc
  clk: mmp2-audio: add missing PM_CLK dependency
  clk: zte: Introduce a driver for zx297520v3 LSP clocks
  clk: zte: Introduce a driver for zx297520v3 matrix clocks
  clk: zte: Introduce a driver for zx297520v3 top clocks
  clk: zte: Add zx PLL support infrastructure
  clk: zte: Add regmap-based clocks
  clk: zte: Add Clock registration infrastructure
  dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
  clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
  ...

1 files changed, 15 insertions, 0 deletions

diff --git a/rust/kernel/clk.rs b/rust/kernel/clk.rs
index 7abbd0767d8c..f04f5c4a03d6 100644
--- a/rust/kernel/clk.rs
+++ b/rust/kernel/clk.rs
@@ -35,16 +35,31 @@ impl Hertz {
     const GHZ_TO_HZ: c_ulong = 1_000_000_000;
 
     /// Create a new instance from kilohertz (kHz)
+    ///
+    /// # Panics
+    ///
+    /// Panics if `CONFIG_RUST_OVERFLOW_CHECKS` is enabled and `khz` is greater
+    /// than `c_ulong::MAX / 1_000`.
     pub const fn from_khz(khz: c_ulong) -> Self {
         Self(khz * Self::KHZ_TO_HZ)
     }
 
     /// Create a new instance from megahertz (MHz)
+    ///
+    /// # Panics
+    ///
+    /// Panics if `CONFIG_RUST_OVERFLOW_CHECKS` is enabled and `mhz` is greater
+    /// than `c_ulong::MAX / 1_000_000`.
     pub const fn from_mhz(mhz: c_ulong) -> Self {
         Self(mhz * Self::MHZ_TO_HZ)
     }
 
     /// Create a new instance from gigahertz (GHz)
+    ///
+    /// # Panics
+    ///
+    /// Panics if `CONFIG_RUST_OVERFLOW_CHECKS` is enabled and `ghz` is greater
+    /// than `c_ulong::MAX / 1_000_000_000`.
     pub const fn from_ghz(ghz: c_ulong) -> Self {
         Self(ghz * Self::GHZ_TO_HZ)
     }