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| author | Timur Kristóf <timur.kristof@gmail.com> | 2026-05-13 22:04:08 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-05-19 12:10:13 -0400 |
| commit | 4d798ea0712fddbd35b439cef32b8ac735eb76f9 (patch) | |
| tree | 26b763231876aa715dc0289ee307babbad5252b2 /scripts/cleanpatch | |
| parent | 48b13bfbdf94e683cc5b8c5cb35b5af4221e657f (diff) | |
drm/amdgpu: Align amdgpu_gtt_mgr entries to TLB size on Tahiti (v2)
The TLB is organized in groups of 8 entries, each one is 4K.
On Tahiti, the HW requires these GART entries to be 32K-aligned.
This fixes a VCE 1 firmware validation failure that can happen
after suspend/resume since we use amdgpu_gtt_mgr for VCE 1.
v2:
- Change variable declaration order
- Add comment about "V bit HW bug"
Fixes: 698fa62f56aa ("drm/amdgpu: Add helper to alloc GART entries")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 530411b465ef0b2c0cc18c2e3d7e38422b1117d1)
Diffstat (limited to 'scripts/cleanpatch')
0 files changed, 0 insertions, 0 deletions