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authorParthiban Veerasooran <parthiban.veerasooran@microchip.com>2025-10-30 15:52:58 +0530
committerJakub Kicinski <kuba@kernel.org>2025-10-31 16:52:06 -0700
commit07f5765f26c3c7381a59d37c73d3ec51b4fd5cf0 (patch)
tree3962f33e0931c26749a39d1074056a343e011bf3 /scripts/objdiff
parente7e756779afa102fc8f9d648ccdc2ecbc41ce2f8 (diff)
net: phy: microchip_t1s: configure link status control for LAN867x Rev.D0
Configure the link status in the Link Status Control register for LAN8670/1/2 Rev.D0 PHYs, depending on whether PLCA or CSMA/CD mode is enabled. When PLCA is enabled, the link status reflects the PLCA status. When PLCA is disabled (CSMA/CD mode), the PHY does not support autonegotiation, so the link status is forced active by setting the LINK_STATUS_SEMAPHORE bit. The link status control is configured: - During PHY initialization, for default CSMA/CD mode. - Whenever PLCA configuration is updated. This ensures correct link reporting and consistent behavior for LAN867x Rev.D0 devices. Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20251030102258.180061-3-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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