Merge tag 'cxl-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl

Pull CXL updates from Dave Jiang:
 "A collection of CXL fixes and changes, including an update to
  MAINTAINERS to add Ming Li as a CXL subsystem reviewer.

  There's also a series to introduce devm_cxl_probe_mem() core API in
  order to pave the way for CXL type2 device drivers to setup and
  retrieve CXL region resource during probe"

* tag 'cxl-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (26 commits)
  cxl: Add dummy function for cxl_memdev_attach_region for !CONFIG_CXL_REGION
  cxl/region: Introduce devm_cxl_probe_mem()
  cxl/memdev: Introduce cxl_class_memdev_type
  cxl/memdev: Pin parents for entire memdev lifetime
  cxl/region: Resolve region deletion races
  cxl/region: Block region delete during region creation
  cxl/region: Fill first free targets[] slot during auto-discovery
  cxl/region: Fix out-of-bounds access in cxl_cancel_auto_attach()
  tools/testing/cxl: Resolve auto-region decoder targets like real HW
  cxl: Align interleave decode/encode helpers with their callers
  cxl/test: Add check after kzalloc() memory in alloc_mock_res()
  cxl/test: Unregister cxl_acpi in cxl_test_init() error path
  cxl/test: Zero out LSA backing memory to avoid leaking to user
  cxl/test: Fix integer overflow in mock LSA bounds checks
  cxl/test: Verify cmd->size_in before accessing payload
  cxl/port: update reference to removed CONFIG_PROVE_CXL_LOCKING
  cxl/region: Avoid variable shadowing in region attach paths
  cxl: Fix CXL_HEADERLOG_SIZE to match RAS Capability size
  cxl/pci: Convert PCIBIOS errors to errno on DVSEC config accesses
  cxl/pci: Fix the incorrect check of pci_read_config_word() return
  ...

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