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authorDave Jiang <dave.jiang@intel.com>2026-01-22 16:59:43 -0700
committerDave Jiang <dave.jiang@intel.com>2026-01-22 16:59:43 -0700
commit914c743509d56067eeeb2b5e341a44a68ef8377d (patch)
tree64c0b0c1b766a8ea4d479f86477afc0dea27b38f /scripts
parent064c098790944fa44f6aa704eb55a5c3ed65a2fa (diff)
parent9a8920ca8ebfb99604f639e7fbc681d0d04518a0 (diff)
Merge branch 'for-7.0/cxl-aer-prep' into cxl-for-next
Preparation for CXL port error protocol handling. First part contains all the changes centered around setting up the PCI side of error handling. cxl: Update RAS handler interfaces to also support CXL Ports cxl/mem: Clarify @host for devm_cxl_add_nvdimm() PCI/AER: Update struct aer_err_info with kernel-doc formatting PCI/AER: Report CXL or PCIe bus type in AER trace logging PCI/AER: Use guard() in cxl_rch_handle_error_iter() PCI/AER: Move CXL RCH error handling to aer_cxl_rch.c PCI/AER: Update is_internal_error() to be non-static is_aer_internal_error() PCI/AER: Export pci_aer_unmask_internal_errors() cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.c PCI/AER: Replace PCIEAER_CXL symbol with CXL_RAS cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c PCI: Replace cxl_error_is_native() with pcie_aer_is_native() cxl/pci: Remove unnecessary CXL RCH handling helper functions cxl/pci: Remove unnecessary CXL Endpoint handling helper functions PCI: Introduce pcie_is_cxl() PCI: Update CXL DVSEC definitions PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h
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