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authorMagnus Lindholm <linmag7@gmail.com>2026-10-09 01:14:29 +0200
committerMagnus Lindholm <linmag7@gmail.com>2026-10-18 20:43:28 +0200
commitea2b073b4f31f334354479b993160788610c779d (patch)
tree7ae8ef4dd0e443d18015173c8739756de495210b /scripts
parenta182df7ceae5d75a7fdc5dc211ccebdd821697bf (diff)
alpha: decode and acknowledge Tsunami system machine checks
Decode PCI and ECC transactions separately, honor invalid transaction information, and select Pchip errors using the logout summary. Report master aborts without importing Titan-specific dismissal policy. Delegate processor vectors to the bounded EV6 decoder. On system vectors 660/620, capture live PERROR and MISC before acknowledging their defined W1C bits and report live status absent from the saved frame. Leave live chipset registers alone on CPU and environmental vectors: HRM 10.2.5.6 warns that PERROR can have INV set before the error reaches DRIR. Consuming that state from a CPU vector could lose the transaction and its pending system-error notification. Leave PERRMASK as configured by firmware. HRM 10.2.5.7 says a cleared mask bit prevents the corresponding PERROR bit from being set, including by PERRSET. Table 10-43 gives a reset value of zero, so this reporting depends on firmware enabling the errors; changing masks does not establish that previously latched state is cleared. Table 10-42 marks PERROR bit 9 reserved (MBZ/RAZ); remove the obsolete RTO definition and reserve its bitfield. Use the system vector and frame bounds without restricting the reason code to the ES40 values. Preserve invalid frames and unknown environmental layouts in bounded raw dumps. Print CPU registers for uncorrectable system errors, including the PC needed to diagnose NXM. Gate correctable system register dumps on CONFIG_VERBOSE_MCHECK and alpha_verbose_mcheck while retaining their error decode. Keep transaction information unavailable whenever SERR is set, as required by HRM 8.8.2.6. Table 10-42 selects ECC fields for CRE/UECC. The first error freezes PERROR and only LOST can be set afterwards, so mixed error bits were detected together. The expected-probe path has no active Tsunami writer. Reporting and acknowledgment do not establish recovery; panic policy remains separate. Signed-off-by: Magnus Lindholm <linmag7@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Magnus Lindholm <linmag7@gmail.com>
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