diff options
| author | Terry Bowman <terry.bowman@amd.com> | 2026-01-30 16:04:01 -0800 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-02-02 08:45:57 -0700 |
| commit | ef1df6cf69785ec6c949ecfa92c49cfc5e237576 (patch) | |
| tree | 6085a67a60496ff4d48cb2a799f5a2e1f6f79ff0 /scripts | |
| parent | 7f5ff740ce0bcde242dafcc3f9bb3cbe6b5b8f3a (diff) | |
cxl/port: Map Port RAS registers
In preparation for CXL VH (Virtual Host) topology protocol error handling,
add RAS capability registered mapping for all ports in a CXL VH topology.
This includes the RAS capabilities of Switch Upstream Ports, Switch
Downstream Ports, Host Bridge Ports ("upstream"), and Root Ports
("downstream")
Update cxl_port_add_dport() to map the upstream RAS capability on first
'dport' attach.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Co-developed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Tested-by: Terry Bowman <terry.bowman@amd.com>
Link: https://patch.msgid.link/20260131000403.2135324-8-dan.j.williams@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions