diff options
| author | Linus Walleij <linusw@kernel.org> | 2026-09-10 21:05:39 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2026-10-14 17:22:02 +0100 |
| commit | f8ebc827f2b0aed23295886543c0823c908dcee1 (patch) | |
| tree | 32912529d7ac6e7cd5939f0c419a52580823e7ec /scripts | |
| parent | cee9395acd8043be0644b25c34bfa86623f2b935 (diff) | |
ARM: 9482/5: decompressor: always set endianess on xscale
In BE32 configurations, endianess is always set to BE in Control
Register C1, originally to allow booting BE kernels from a LE bootloader
on IXP12xx.
To also allow the opposite and allow booting LE kernels from a BE
IXP4xx bootloader, moving this code into head-xscale.S along with the
recommended serialization sequence and flip the B bit into the correct
position regardless of its original state.
Note that both the endianess switch sequence and the cp15wait I add
here should be harmless on all supported ARMv4/v4t/v5 CPUs, but the
existing cache flush code is not actually defined on ARM720 and may
cause problems in multiplatform kernels that include both Xscale
and CLPS711x.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions