diff options
| author | Nicolin Chen <Guangyu.Chen@freescale.com> | 2014-04-30 18:54:05 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-05-05 12:26:05 -0700 |
| commit | 9c6344b3fa547ce7ec78da95134d92d9f9309b31 (patch) | |
| tree | 4fc10c4e0474c45a7facd093949e3c822bff94b7 /sound/soc/fsl/fsl_spdif.h | |
| parent | 0b8643900a1bff32ad8bf17ef1f5d57b6d490502 (diff) | |
ASoC: fsl_spdif: Use clk_set_rate() for spdif root clock only
The clock mux for the Freescale S/PDIF controller has eight clock sources
while most of them are from other moudles and even system clocks that do
not allow a rate-changing operation.
So we here only allow the clk_set_rate() and clk_round_rate() happened to
spdif root clock, the private clock for S/PDIF controller.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc/fsl/fsl_spdif.h')
| -rw-r--r-- | sound/soc/fsl/fsl_spdif.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sound/soc/fsl/fsl_spdif.h b/sound/soc/fsl/fsl_spdif.h index b1266790d117..18bf8cdc579e 100644 --- a/sound/soc/fsl/fsl_spdif.h +++ b/sound/soc/fsl/fsl_spdif.h @@ -157,6 +157,8 @@ enum spdif_gainsel { #define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK) #define STC_TXCLK_SRC_MAX 8 +#define STC_TXCLK_SPDIF_ROOT 1 + /* SPDIF tx rate */ enum spdif_txrate { SPDIF_TXRATE_32000 = 0, |