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| author | Mario Limonciello <mario.limonciello@amd.com> | 2026-09-15 12:52:41 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-09-17 11:38:29 -0400 |
| commit | 15b2b067445617f4f789f56cc566a72f88d72345 (patch) | |
| tree | 70fbf8fc2ec7461e7593f852d10a04ed06f7809a /tools/lib/python/kdoc/parse_data_structs.py | |
| parent | 4ac1835823c47903fbb278bbf474773c46f59edc (diff) | |
drm/amdgpu: Reuse cached PCIe link device
After "drm/amdgpu: Fix GPU PCIe link capability reporting" there are
now a few areas of walking topology.
Use the cached GPU-side link device for ASPM queries and switch state
caching instead of walking the PCI topology independently in each path.
Validate the internal downstream/upstream switch pair when initializing
the cached link devices so all consumers share the existing topology
checks.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/lib/python/kdoc/parse_data_structs.py')
0 files changed, 0 insertions, 0 deletions