drm/amd/display: Force DSC to 8bpp for MST DP tunneling over USB4

Commit "drm/amd/display: Force DSC to 8bpp for SST DP tunneling over USB4"
forces DSC and caps the target to 8 bpp for SST streams on a USB4 DPIA
link with bandwidth allocation enabled.  The MST DSC fairness path does
not honor that policy: it derives the bpp range purely from the timing's
DSC policy and picks the highest bpp the native DP link can carry, which
overflows the smaller USB4 tunnel budget on a dock that fans out via an
internal MST hub.

Apply the equivalent policy in compute_mst_dsc_configs_for_link(): when
the link is a USB4 DPIA with BW allocation enabled, force DSC on
(so the fairness pass does not leave a stream uncompressed just because
the native link looks large enough) and pin the target to the minimum
bpp (so the compressed stream fits the tunnel and reserves headroom for
the other tunnels on the same host router).

Reviewed-by: Roman Li <roman.li@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

0 files changed, 0 insertions, 0 deletions