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authorJakub Kicinski <kuba@kernel.org>2026-10-02 13:08:57 -0700
committerJakub Kicinski <kuba@kernel.org>2026-10-02 13:08:58 -0700
commitcfb7793d1bc0f7d90571611979654cf1b3886b29 (patch)
treebf0b3d6c32605541ae18af2ae8a980e1e973ef8c /tools/lib/python/kdoc/python_version.py
parent4841fb8f557d090b37900f9179d3ff668f678b16 (diff)
parent14b9ac2f189db8809a3c9f750d7700cfc9d21f77 (diff)
Merge branch 'net-lan966x-add-support-for-pcie-fdma'
Daniel Machon says: ==================== net: lan966x: add support for PCIe FDMA When lan966x operates as a PCIe endpoint, the driver currently uses register-based I/O for frame injection and extraction. This approach is functional but slow, topping out at around 33 Mbps on an Intel x86 host with a lan966x PCIe card. This series adds FDMA (Frame DMA) support for the PCIe path. When operating as a PCIe endpoint, the internal FDMA engine on lan966x cannot directly access host memory, so DMA buffers are allocated as contiguous coherent memory and mapped through the PCIe Address Translation Unit (ATU). The ATU provides outbound windows that translate internal FDMA addresses to PCIe bus addresses, allowing the FDMA engine to read and write host memory. Because the ATU requires contiguous address regions, page_pool and normal per-page DMA mappings cannot be used. Instead, frames are transferred using memcpy between the ATU-mapped buffers and the network stack. With this, throughput increases from ~33 Mbps to ~620 Mbps for default MTU. Patch 1 adds the shared drivers/net/ethernet/microchip/fdma/ directory to the Sparx5 SoC MAINTAINERS entry. Patches 2-4 prepare the shared FDMA library: patch 2 renames the contiguous dataptr helpers for clarity, patch 3 adds PCIe ATU region management and coherent DMA allocation with ATU mapping, and patch 4 gives the descriptor fields an explicit little-endian type, since on the PCIe path the descriptors are written by the host CPU. Patches 5-8 refactor the lan966x FDMA code to support both platform and PCIe paths: extracting the LLP register write into a helper, exporting shared functions, introducing a dedicated device for DMA operations, and adding an ops dispatch table selected at probe time. Patches 9-10 harden the existing FDMA path for the PCIe endpoint lifecycle: patch 9 clears latched FDMA error/interrupt stickies after the switch reset so they don't assert as soon as interrupts are enabled, and patch 10 adds a shutdown() callback that quiesces the FDMA engine on host warm reboot (on the PCIe card the FDMA survives host reset and would otherwise keep the shared INTx asserted into the next probe). Patch 11 adds the core PCIe FDMA implementation with RX/TX using contiguous ATU-mapped buffers. Patches 12 and 13 extend it with MTU change and XDP support respectively. XDP_PASS, XDP_TX, XDP_DROP and XDP_ABORTED are supported; XDP_REDIRECT is deliberately not, because the PCIe data path does not use page_pool. Patches 14-15 update the lan966x PCI device tree overlay to extend the cpu register mapping to cover the ATU register space and add the FDMA interrupt. Patches 1-13 touch MAINTAINERS and drivers/net/ethernet/microchip/, and are for the netdev tree. Patches 14-15 touch drivers/misc/lan966x_pci.dtso, and are for the char-misc tree. ==================== Link: https://patch.msgid.link/20260928-lan966x-pci-fdma-v9-0-a17caf60f89a@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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