firmware: stratix10-svc: add Agilex5 SMMU DMA coherent support

On Agilex5, DDR starts at 0x8000_0000 which is outside the SDM's
addressable range. When SMMU is active, the driver must allocate
DMA-coherent buffers and pass IOVAs (not physical addresses) to ATF.

Add SVC_SDM_DMA_ADDR_BITS (29) and SVC_SDM_DMA_ADDR_OFFSET
(0x8000_0000) to constrain IOVAs to the 0-512 MB window the SDM can
reach and to satisfy ATF's address range check respectively.

Extend struct stratix10_svc_data_mem with dma_addr, and
struct stratix10_svc_controller with use_dma_mem and dma_addr_offset.
Update allocate/free and svc_thread_cmd_data_claim() for the DMA path.

Wire the Agilex5 path in probe: require an IOMMU domain for
intel,agilex5-svc, bypass the SDM address remapper via
INTEL_SIP_SMC_SDM_REMAPPER_CONFIG, call svc_setup_dma_memory() to set
the 29-bit DMA mask, select the DMA path through stratix10_svc_pdata,
register a devm cleanup for leaked buffers, and guard err_destroy_pool
against a NULL genpool.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

0 files changed, 0 insertions, 0 deletions