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authorYongxing Mou <yongxing.mou@oss.qualcomm.com>2026-09-29 12:25:31 +0800
committerDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>2026-10-01 15:12:29 +0300
commit5e4a3f7b262060d70cfdc7889cfe0f4aba9ea3fc (patch)
tree02b0ddbb5555cc7f64b9e000a096c9d3a74c9a1d /tools/lib/python/kdoc
parentcb821ad0df17f9c42d003bb9457fc83c89ba4081 (diff)
drm/msm/dp: add stream-aware link register accessors
DisplayPort MST uses multiple stream-specific register spaces. Streams 0 and 1 share the primary link register block with different register offsets, while streams 2 and 3 use dedicated MST link register blocks. Add stream-aware register access helpers that translate stream-specific register offsets and route accesses to the appropriate register space based on the stream id. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/756910/ Link: https://lore.kernel.org/r/20260929-msm-dp-mst-v7-7-4b81473185e7@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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