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| author | Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> | 2026-09-11 17:04:52 +0800 |
|---|---|---|
| committer | Rob Herring (Arm) <robh@kernel.org> | 2026-11-02 13:25:21 -0600 |
| commit | 9c1075791172d936935ca20d7f0c1da601c4f408 (patch) | |
| tree | 1469ea1e527c516926deb50ef6cb42e8a745fa47 /tools/lib/python | |
| parent | b08bd567165dcff9d99cc6842b27429f9370158a (diff) | |
dt-bindings: usb: add Altera Agilex5 DWC3 controller
Add a binding for the Altera Agilex5 SoC integration of the Synopsys DWC3
USB controller (compatible "altr,agilex5-dwc3"), covering clocks, resets,
PHYs, and optional IOMMU support.
Clock names follow the snps,dwc3.yaml example order (bus_early, ref,
suspend). Reset names use core/ecc. On this SoC ref and suspend are the
same hardware source, so the example reuses AGILEX5_USB31_SUSPEND_CLK.
Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/0fbda23eb4a22a56e455b5e89125813af60ab0cc.1789114385.git.adrian.ho.yin.ng@altera.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions