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| author | Eliot Courtney <ecourtney@nvidia.com> | 2026-08-27 17:51:45 +0900 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2026-09-07 11:54:36 +0900 |
| commit | b05ff82081b7b90fdd70cc7d07b3da9d85184f88 (patch) | |
| tree | 68c1d7e2ff2cc3ca4e0659e8bb5ebd1c3f610be7 /tools/lib/python | |
| parent | d3bd73dcf51d88ae116a574ce2f49209c7b48944 (diff) | |
gpu: nova-core: mm: Add the memory management HAL
Positioning the PRAMIN window requires writing an architecture-specific
register: `NV_PBUS_BAR0_WINDOW` on Turing, Ampere and Ada, and
`NV_XAL_EP_BAR0_WINDOW` with a different field width on Hopper and on
Blackwell.
A `MmHal` trait with one implementation per hardware family hides the
register choice from the rest of the mm code, matching the layout of
the driver's other HALs.
Signed-off-by: Eliot Courtney <ecourtney@nvidia.com>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260827-pramin-split-v3-4-24b24d7afc52@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions