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authorSascha Bischoff <Sascha.Bischoff@arm.com>2026-09-04 11:44:56 +0000
committerMarc Zyngier <maz@kernel.org>2026-09-14 10:49:08 +0100
commitc7f62066f2cf452043b43fbb7af179411029eff6 (patch)
treef56e0d959eb04e5d61570aedceb8fa1cb57e33c6 /tools/lib/python
parentf116c96e451b66831e05807d8a75259db041d2a5 (diff)
KVM: arm64: gic-v5: Initialise per-VM IRS state
A virtual GICv5 needs an emulated IRS in addition to the host IRS state used to back VMTEs, VPEs, and ISTs. Without this, KVM can only provide the CPU-local PPI state and cannot expose the IRS-backed SPI and LPI configuration expected by a GICv5 guest. Allocate the per-VM emulated IRS state when creating a virtual GICv5, and initialise it from vgic_v5_init(). If userspace has not provided a number of SPIs, use the GICv5 default of 32. The IRS init path allocates the SPI state, initialises the virtual IRS register state, and creates the backing SPI IST when SPIs are present. Keep the per-VM IRS object alive for the lifetime of the virtual GICv5. vgic_v5_teardown() only unwinds resources allocated by vgic_v5_init(), so failed initialisation can be retried, while kvm_vgic_dist_destroy() frees the IRS object during final VGIC destruction. This gives virtual GICv5s the IRS backing required for SPIs and LPIs, rather than being limited to PPIs only. Further patches add support for SPI injection and lifecycle tracking. Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Link: https://patch.msgid.link/20260904113404.4051341-22-sascha.bischoff@arm.com Signed-off-by: Marc Zyngier <maz@kernel.org>
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