diff options
| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-09-24 07:49:50 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2026-09-29 11:23:08 +0530 |
| commit | c9e608d1247cd4c286a54d7f26188c41e8f0a6c2 (patch) | |
| tree | f5d71536aa94f3950006464d2052aed7423dd888 /tools/lib/python | |
| parent | a8c17ccf9eb85c2b60376bb6ab98d75f897073b9 (diff) | |
drm/i915/display: Update the CMN_SDP_TL in fastset path
Commit bfa597238073 ("drm/i915/dip: Enable Common SDP Transmission line")
enabled the CMN_SDP_TL for the modeset path, but missed to add it to the
fastset path.
Since dip.cmn_sdp_tl is already skipped from the strict pipe-config
comparison during fastsets, it was always intended to get updated
without full modeset, but the update to the register was missed.
During a fastset, if CMN_SDP_TL changes, update the register
similar to the EMP_AS_SDP_TL, which gets updated in
intel_vrr_set_transcoder_timings().
v2: Update cmn_sdp_changed() to also compare gmp_sdp_tl, pps_sdp_tl and
vsc_ext_sdp_tl, not just cmn_sdp_tl. (Sashiko)
Fixes: bfa597238073 ("drm/i915/dip: Enable Common SDP Transmission line")
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260924021950.350207-1-ankit.k.nautiyal@intel.com
Diffstat (limited to 'tools/lib/python')
0 files changed, 0 insertions, 0 deletions