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| author | Austin Kim <austin.kim@lge.com> | 2026-01-25 21:08:59 -0700 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-01-25 21:08:59 -0700 |
| commit | 494d4a051c3bfc79b847a46bdc52a2473d27b3b0 (patch) | |
| tree | ee13b1eb5f1abf128cb7f667ea864e5b8eb110a1 /tools/perf/python | |
| parent | ba89709a3610ba27a2eef2e127f3f4fc5b64d5f7 (diff) | |
riscv: fix minor typo in syscall.h comment
Some developers may be confused because RISC-V does not have
a register named r0. Also, orig_r0 is not available in pt_regs structure,
which is specific to riscv. So we had better fix this minor typo.
Signed-off-by: Austin Kim <austin.kim@lge.com>
Link: https://patch.msgid.link/aW3Z4zTBvGJpk7a7@adminpc-PowerEdge-R7525
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Diffstat (limited to 'tools/perf/python')
0 files changed, 0 insertions, 0 deletions