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| author | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2026-10-16 16:35:34 +0200 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2026-10-16 16:35:34 +0200 |
| commit | 5d299ec9395e2458fb6d6f4b643340a7ad4ceb5e (patch) | |
| tree | 77e26883f4ef61feab1daf50be12a1be00f64248 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 62c27ed02e298b236d42443e76437da9d181c8ad (diff) | |
| parent | 60e4cafd30908e7d8cdfdb4fa1a74dabed9f47b5 (diff) | |
Merge tag 'riscv-sophgo-dt-for-v7.4' of https://github.com/sophgo/linux into soc/dt
RISC-V Devicetrees for v7.4
Sophgo:
For CV18xx serials:
- Add an overlay to enable MAC and MDIO multiplexer to
reach the internal PHY so we can use Milk-V Duo 256M
board with optional ethernet interface.
- Fix the name of the internal PHY node.
- Drop reserved memory node, and leave FSBL to decide
this at runtime.
For SG2042:
- Limit SPI NOR to 12.5 MHz.
For SG2044:
- Enable both SPI NOR controllers.
Signed-off-by: Chen Wang <chen.wang@linux.dev>
* tag 'riscv-sophgo-dt-for-v7.4' of https://github.com/sophgo/linux:
riscv: dts: sophgo: sg2002-milkv-duo256m: drop reserved memory node
riscv: dts: sophgo: cv1800b-milkv-duo: drop reserved memory node
riscv: dts: sophgo: cv180x: Fix internal ephy node name
riscv: dts: sophgo: add Milk-V Duo 256M ethernet support overlay
riscv: dts: sophgo: Limit SG2042 SPI NOR to 12.5 MHz
riscv: dts: sophgo: Enable SPI NOR on SRD3-10
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions
