mmc: sdhci-of-dwcmshc: Disable CQE error halt request for Rockchip

In CMDQ mode an I/O error in one task (data_crc_err, data_end_bit_err,
etc.) makes the controller raise a halt request. While the halt request
is pending, the controller rejects doorbell writes with a slave response
error, which hangs the CPU (or raises SError on ARM) on Rockchip
platforms.

A software workaround[1] clears CQHCI_CTL right before ringing the
doorbell to narrow down the window, but a race remains: an I/O error can
still happen in another slot between the CQHCI_CTL write and the
doorbell kick, so the hang is not fully solved.

To fix this once and for all, newer silicon introduces
SW_ERR_HALR_REQ_DISABLE (CQHCI_CTL[1]) which stops the controller from
raising a halt request on I/O errors. Set the bit when the CQE is
enabled, which is the last CQHCI_CTL write before any doorbell write.

Older SoCs keep this bit reserved, so writing it is a no-op and nothing
changes in the wild, thus no fixes tag is needed.

[1] https://github.com/rockchip-linux/kernel/commit/4b7ea0500a1a5c186807b737fecfc6bb4d4e06f8
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulfh@kernel.org>

0 files changed, 0 insertions, 0 deletions