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authorXiaofeng Yuan <yuanxiaofeng@eswincomputing.com>2026-09-17 20:14:11 +0800
committerAnup Patel <anup@brainfault.org>2026-10-10 13:29:55 +0530
commitbae99073549aba7c3d79685a4640a46aa5c55340 (patch)
treefcfd42ec280d75d8aeb3222a17e9f7d586cc00f8 /tools/perf/scripts/python/bin/stackcollapse-report
parentc367d3bf721f2bc391d6cfb47f6884e99d563df0 (diff)
RISC-V: KVM: Replace imsic switch-case macros with range checks
The imsic_eix_read/swap/write/set accessors use a family of macros that expand into a switch with 128 cases covering the EIP and EIE register windows. This mirrors the csr_read_num() idiom required where a CSR number must be encoded as a csrr instruction immediate (e.g. drivers/perf/riscv_pmu.c), but here the register number is merely written to vsiselect as data, so the expansion solves no real constraint. It costs ~90 lines of nested macros and trips ~30 checkpatch errors and warnings. Since the generated cases form two contiguous windows, [IMSIC_EIP0, IMSIC_EIP63] and [IMSIC_EIE0, IMSIC_EIE63], the same behavior is expressed with a simple range check. Introduce imsic_eix_ireg_is_valid() and use it in the four accessors, removing the macros along with the ~30 checkpatch errors and warnings they caused. No functional change intended. Compile tested with riscv64-linux-gnu-gcc and tested on QEMU (RISC-V virt, AIA). Signed-off-by: Xiaofeng Yuan <yuanxiaofeng@eswincomputing.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260917121411.2445-1-yuanxiaofeng@eswincomputing.com Signed-off-by: Anup Patel <anup@brainfault.org>
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