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authorSahaj Chaudhari <sahaj123.sc@gmail.com>2026-10-15 12:13:41 +0530
committerMark Brown <broonie@kernel.org>2026-10-15 13:51:12 +0100
commitc126e07bde21c518f1356937ac240500d1bc81c0 (patch)
treec3e9877d75e91ad4ad055f417a068b5254938b77 /tools/perf/scripts/python/bin/stackcollapse-report
parent7db773075501248893c22b11bedc6745d6d0be45 (diff)
spi: omap2-mcspi: handle DMA setup failures
The DMA paths ignore failures from dmaengine_slave_config(), descriptor preparation and dmaengine_submit(), and carry FIXME comments about falling back to PIO. A failed setup can leave a half-started transfer or wait for a completion that never arrives. Check each step and clean up with dmaengine_terminate_sync() on error. Prepare both descriptors before issuing either channel. Fall back to PIO only for host-mode transfers that have a TX buffer, when no DMA has been started and cleanup succeeded. RX-only and target-mode transfers return the error instead, since the bus may already be clocking. The FIFO is enabled before the DMA attempt, but the PIO path polls per-word TXS/RXS and does not expect FIFO mode. Disable the FIFO, with the channel off while its bits change, before falling back. Tested on an AM642 board with a TI 6.12.57 vendor kernel built with this patch and booted from RAM. On a McSPI bus using DMA, 200 iterations of 4096-byte TX and 1024-byte RX spidev transfers completed with no errors, timeouts or kernel warnings. With a temporary change that fails every DMA-sized TX setup, 60 spidev writes fell back to PIO with no errors or timeouts. That test used a bus with no device attached and did not show a difference with and without the FIFO disable, which is based on reading the code. Fixes: 53741ed8f0a3 ("spi: omap2-mcspi: add DMA engine support") Link: https://lore.kernel.org/r/20250914022132.319227-1-alex.t.tran@gmail.com Signed-off-by: Sahaj Chaudhari <sahaj123.sc@gmail.com> Link: https://patch.msgid.link/20261015064341.1100422-1-sahaj123.sc@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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