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| author | Thierry Reding <treding@nvidia.com> | 2026-09-02 12:17:37 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2026-10-01 15:53:29 +0200 |
| commit | fd6377c033ef58740e2898a96cabb442157aee0a (patch) | |
| tree | 6d54effb12c9948e91b1eef4034c46d1f5f217d0 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | a3dbfe954fd7b741e2d082e0378780c15123da90 (diff) | |
ARM: tegra: Clean up AHUB on Tegra124
Use #address-cells = <1> and #size-cells = <1> because we don't need
64-bit register addressing for this hardware. While at it, also adjust
the ranges property to encompass the entire AHUB range as per the TRM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions