diff options
| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2026-09-16 17:40:42 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-09-24 18:00:31 +0100 |
| commit | 92871abc1302b852b88d86114115f8fd6b50b9b9 (patch) | |
| tree | eda2f022dc6447ef709f6ac1515be242fd1c9e65 /tools/perf/scripts/python/bin | |
| parent | db1761980ccc3b792dbd6e106c237d06108ea897 (diff) | |
ASoC: fsl_asrc: use regmap_write_bits to update clock source registers
After a warm reboot the REG_ASRCSR register may not be in its hardware
reset state. regmap caches the register value as 0 (the assumed default),
so when the desired clock source index is also 0, regmap_update_bits()
skips the actual hardware write because it believes the register already
holds the correct value. This leaves a stale clock source in the hardware.
Replace regmap_update_bits() with regmap_write_bits() so that the masked
fields are always written to hardware regardless of the cached value.
Fixes: 3117bb3109dc ("ASoC: fsl_asrc: Add ASRC ASoC CPU DAI and platform drivers")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Chancel Liu <chancel.liu@nxp.com>
Link: https://patch.msgid.link/20260916094043.1496709-1-shengjiu.wang@oss.nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions
