mmc: sunplus: initialise rd_crc_dly=1 for DDR modes

After spmmc_controller_init() resets the controller, all timing
fields are zero.  The hs_en path initialises the write timing
delays (wr_cmd_dly, wr_dat_dly) but leaves the read side at zero.

In DDR52 mode, rd_crc_dly=0 causes the first write to fail with
CRC_TOKEN_CHECK_ERROR, triggering the auto-tuning retry loop and
causing a multi-second delay on the first cold-boot write.

Set rd_crc_dly=1 when enabling DDR mode to avoid this.

Tested on a LTPP3G2, booting via eMMC in DDR52 mode,
on linux-next-20260915.

Signed-off-by: Andrew Gaylard <ag@ffroot.co.za>
Signed-off-by: Ulf Hansson <ulfh@kernel.org>

0 files changed, 0 insertions, 0 deletions