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authorNicolo Giuliani <nicolo.giuliani6@studio.unibo.it>2026-09-21 02:26:43 +0200
committerGregory CLEMENT <gregory.clement@bootlin.com>2026-09-30 21:52:13 +0200
commit0f72e965efec4cda7c3b1ac76edfab53f27ed9a7 (patch)
tree94969e01779c5cd6482f442e140651ab5a159b1d /tools/perf/scripts/python/export-to-postgresql.py
parent1e00af6b081d3854679638972f03b38886679a18 (diff)
arm64: dts: marvell: Add Sophos XGS 107w NPU board
Add a device tree for the network processing unit (NPU) of the Sophos XGS 87/107 desktop firewalls. The appliance pairs an AMD x86 host with the NPU, a Marvell Armada CN9130 SoC with its own eMMC and SPI NOR flash that runs independently of the host and serves the front panel ports. The eight RJ45 ports and the SFP cage are connected through a Marvell 88E6193X switch on the MDIO bus of the SoC, at address 2. Switch port 0 is the CPU port, a 10GBASE-R link to the first mvpp2 port. Ports 1 to 8 are the RJ45 ports, which use the internal PHYs of the switch, and port 9 is the SFP cage, connected over 1000BASE-X. Describe the UART console, the eMMC, the SPI NOR flash that holds the boot loader and its environment (read-only), the SFP cage and the switch with its ports. The port LEDs, the PCIe link to the x86 host and the USB ports are not described. The switch is reset through CP GPIO2 pin 17. Tested on an XGS 107w with Linux 6.18: boot from eMMC, eMMC and SPI NOR access, the mvpp2 link to the switch at 10 Gb/s, the 88E6193X probing with its eight user ports, and 936 Mbit/s through a front port. The SFP cage is untested. Assisted-by: LLM Signed-off-by: Nicolo Giuliani <nicolo.giuliani6@studio.unibo.it> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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