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| author | Judith Mendez <jm@ti.com> | 2026-09-09 16:47:41 -0500 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2026-09-22 08:58:41 -0500 |
| commit | dbe55d5f2930b27e9a3ce71f0c9b1bb0ad91a012 (patch) | |
| tree | f782abc0b2105fb1fa49fa3ca610072b715298d9 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | f9a93fe78d8737860a8fb786d17c9dff20782b7d (diff) | |
arm64: dts: ti: k3-am625-var-som-symphony: Set SD clock pins as OUTPUT
MMC clock pins must be configured as OUTPUT-only per TRM [0] with
receiver disabled (RXACTIVE bit = 0). Change MMC CLK pins from
PIN_INPUT to PIN_OUTPUT to match documentation.
[0] https://www.ti.com/lit/pdf/spruiv7 Rev. C: Table 12-246. MMCSDi I/O Signals
Fixes: acb4cd35dbd2 ("arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board")
Cc: stable@vger.kernel.org
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Stefano Radaelli <stefano.r@variscite.com>
Reviewed-by: Moteen Shah <m-shah@ti.com>
Link: https://patch.msgid.link/20260909214743.899477-14-jm@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions