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authorBiju Das <biju.das.jz@bp.renesas.com>2026-08-26 13:27:23 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2026-09-02 14:40:34 +0200
commit8770b189131168ca56e8a3e3850210727a20fb8d (patch)
treeb1a1b15d1e3933a5a52116d4f158dd64a6e6beb1 /tools/perf/scripts/python/flamegraph.py
parentb7453d3fbb017069466fcd4a0d50ffcfeadaee84 (diff)
soc: renesas: rz-sysc: Register auxiliary device for PWRRDY power sequencer
Some RZ SoCs (e.g. RZ/G3L) have a PWRRDY register that is controlled through a power sequencer rather than directly by the SYSC driver. Add a pwrrdy_pwrseq flag to struct rz_sysc_soc_id_init_data to mark SoCs with this property, and set it for RZ/G3L. When set, rz_sysc_probe() registers a "pwrseq-pwrrdy" auxiliary device so a dedicated driver can handle the PWRRDY sequencing. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260826122742.153643-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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