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authorAlex Elder <elder@riscstar.com>2026-09-02 16:43:16 -0500
committerBjorn Andersson <andersson@kernel.org>2026-09-03 09:40:12 -0500
commitaaedd4ea312d6fd70dfc5cf430edf5106c5b3382 (patch)
tree1bf85ff6887384d90885c7e9ab02ffef2f7b5c63 /tools/perf/scripts/python/flamegraph.py
parentdf4107fc729e3bffce27fe0ed06fc6a64dd675cd (diff)
arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: clean up PCI function nodes
The qcs6490-rb3gen2-industrial-mezzanine overlay defines two nodes representing TC956x chips, each of which contains a PCIe switch and an embedded endpoint that implements two PCIe functions. The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes. In addition, only PCI bridge nodes should be named "pcie@" (or "pci@"). PCI endpoint nodes are typically named based on the functionality they implement (e.g., "ethernet@"). In this case, the role of these PCI functions is not (yet) specified, and furthermore they will be used with PCI endpoint buses. Rename these to use "dev@", following the convention used in of_pci_make_dev_node() for dynamically-created devicetree nodes. Finally, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove these properties as well; they can be added back once they are actually needed/used. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Fixes: 4559b435f741b ("arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0") Signed-off-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/r/20260902214321.1721477-3-elder@riscstar.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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