arm64: errata: Add NXP i.MX8QM/8QP workaround for A53 cache coherency issue

According to NXP errata document IMX8_1N94W[1], the i.MX8QuadMax and
i.MX8QuadPlus SoCs suffer from a cache coherency issue (ERR050104). The
upper bits, above bit 35, of the ARADDR and ACADDR buses within the Arm
A53 subsystem have been incorrectly connected. This causes some TLBI and
IC maintenance operations exchanged between the A53 and A72 core
clusters to be corrupted.

The workaround requires:

  - Downgrading targeted TLBI operations to broadcast-all variants.
    Instead of patching the low-level __TLBI_1 macro (which causes
    excessive over-invalidation), redirect high-level TLB flush
    functions (flush_tlb_mm, __do_flush_tlb_range,
    flush_tlb_kernel_range, __flush_tlb_kernel_pgtable) to use VMALLE1IS
    via alternatives.

  - Upgrading IC IVAU to IC IALLUIS for both kernel (via ALTERNATIVE in
    invalidate_icache_by_line) and EL0 userspace (via trap-and-upgrade
    in user_cache_maint_handler with SCTLR_EL1.UCI=0).

  - Disabling KVM since correct TLB maintenance cannot be guaranteed
    for guests.

  - No need to touch SMMU Broadcast TLB Maintenance (BTM) since the
    arm-smmu driver does not use it.

SoC detection uses devicetree compatible string "fsl,imx8qm" or
"fsl,imx8qp" since the boot CPU MIDR_EL1 (0x410fd034) and AIDR_EL1 (0)
are not unique to these SoCs.

[1] https://www.nxp.com/docs/en/errata/IMX8_1N94W.pdf

[ Reworked per review feedback from Will Deacon and Mark Rutland:
  - Move TLBI workaround from __TLBI_1 macro to high-level flush
    functions to avoid excessive over-invalidation
  - Add kernel IC IVAU upgrade via ALTERNATIVE in assembler.h
  - Add cpucap_is_possible() entry for compile-time elimination]

Tested-by: Franz Schnyder <franz.schnyder@toradex.com> # Toradex Apalis iMX8QM
Co-developed-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
[catalin.marinas@arm.com: Kconfig and errata text, sysreg_clear_set(), of_machine_compatible_match()]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

0 files changed, 0 insertions, 0 deletions