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| author | Brandon Brnich <b-brnich@ti.com> | 2026-09-21 13:48:50 -0500 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2026-09-28 11:56:24 -0500 |
| commit | 330236fda4fd7a63e3bf9d9ce1b7ce227ddb8f1c (patch) | |
| tree | 413d5250b87f401b84400edcf27265e3bb116f12 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 0bd8ecba297bd50fe5b154a96f6eaf0233b28dd3 (diff) | |
arm64: dts: ti: k3-am62p-j722s-common-main: Assign SRAM to VPU node
The Wave5 VPU supports connecting to on-chip SRAM through its secondary
AXI interface. This allows temporal buffers to be stored on a per-stream
basis, reducing DDR memory traffic.
Signed-off-by: Brandon Brnich <b-brnich@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Link: https://patch.msgid.link/20260921184850.3810018-5-b-brnich@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions