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authorMd Sadre Alam <md.alam@oss.qualcomm.com>2026-08-07 22:05:32 +0530
committerBjorn Andersson <andersson@kernel.org>2026-09-25 14:39:20 -0500
commit4d36e6d8c5a489c85d9440fc7330beee9b74f6f0 (patch)
tree7fee6b6fa35065dca474a042274b052859ea64ab /tools/perf/scripts/python/stackcollapse.py
parent1f6925d80ae327ab4e18e21b7c87c57b793c462c (diff)
arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND
Enable quad SPI transfers for the SPI-NAND device by setting both spi-rx- bus-width and spi-tx-bus-width to 4. Without these properties, the device uses the default single-bit bus width. Configure the board to use 4-bit read and write transfers so the controller and flash can operate in quad SPI mode. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com> Link: https://patch.msgid.link/20260807-quad_dts-v2-2-6f578d4152b7@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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