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| author | Shawn Lin <shawn.lin@rock-chips.com> | 2026-10-09 17:09:57 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2026-10-10 13:11:46 +0200 |
| commit | 5f48abc96182700a006b25b9bfbf80c19455760a (patch) | |
| tree | d84d461b3df483bf5d9ae9e76252fa88e9069ba4 /tools/perf/scripts/python/stackcollapse.py | |
| parent | fc411363b8231315e5260662bac5223636321983 (diff) | |
arm64: dts: rockchip: add pcie30phy data-lanes on rk3588 coolpi-cm5-evb
Both pcie3x2 (PHY port1) and pcie3x4 (PHY port0) are enabled, but
pcie30phy had no data-lanes. Without it the PHY defaults to aggregation
mode and assigns all four lanes to port0, leaving pcie3x2 without lanes
and unable to establish a link. Set data-lanes = <1 1 2 2> to split the
lanes as 2+2 between the two controllers.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1791536997-182608-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions