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| author | Thierry Reding <treding@nvidia.com> | 2026-09-01 21:55:02 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2026-09-11 12:29:39 +0200 |
| commit | 5fa7fe92018dc8fb41b2bd0f9dbbc6e704e795d3 (patch) | |
| tree | 56e81c30bc7438930e7f3cb5cc9614280667bc5c /tools/perf/scripts/python/stackcollapse.py | |
| parent | 3ef40e9e7e52c171c7775fd9fba602290283ac1a (diff) | |
arm64: tegra: Clean up AHUB on Tegra186
Use #address-cells = <1> and #size-cells = <1> because we don't need
64-bit register addressing for this hardware. While at it, also adjust
the ranges property to encompass the entire AHUB range as per the TRM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions