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authorSascha Bischoff <Sascha.Bischoff@arm.com>2026-09-04 11:58:41 +0000
committerMarc Zyngier <maz@kernel.org>2026-09-14 10:49:10 +0100
commit7bebd949670bb5ab1bd14a67779fd308795e247b (patch)
tree913f7d5eb26e3a9d97f78a3f3fb4171597cd0cde /tools/perf/scripts/python/stackcollapse.py
parentfc8ab69c081b99feddf3c873846068013b3a8a78 (diff)
KVM: selftests: Add VGICv5 IST save/restore coverage
Add end-to-end VGICv5 IST save/restore coverage. The earlier IST attribute test checks only API rejection cases; this test verifies that interrupt state saved from the ISTs can be restored into a fresh VM before first run and then consumed by the guest. Build a source VM that configures SPI and LPI enable, priority, and affinity state from the guest. Inject selected SPIs from userspace, save the IRS register state, and save both the SPI and LPI IST images through KVM_DEV_ARM_VGIC_GRP_IST using userspace-provided buffers. Create a restore VM and verify that IST restore is rejected before the IRS state has been restored. Restore the IRS registers, validate bad or missing LPI storage, and restore the saved SPI and LPI IST images. Before the host LPI IST is allocated, verify that userspace can change or invalidate IRS_IST_BASER. Once the IST images have been restored and the host LPI IST exists, verify that matching IRS_IST_BASER and IRS_IST_CFGR values can be replayed, while changing either register or clearing IRS_IST_BASER.Valid is rejected. Before running any destination vCPU, save the ISTs again and compare the re-saved buffers against the original saved buffers so that dropped serialised state fails independently of interrupt delivery. Finally, run the restored guest and check pending and enabled SPI and LPI state across two VPEs, priority ordering through ICC_PCR_EL1, delivery of an interrupt that was pending but disabled at save time, and affinity for interrupts injected after restore. Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Link: https://patch.msgid.link/20260904113404.4051341-49-sascha.bischoff@arm.com Signed-off-by: Marc Zyngier <maz@kernel.org>
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