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| author | Qiang Yu <qiang.yu@oss.qualcomm.com> | 2026-08-19 23:36:54 -0700 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> | 2026-10-13 11:58:05 +0200 |
| commit | 967a73293ae5f57af68e815942078e110c1f6d08 (patch) | |
| tree | 07c79701d825ecb5edd113336fb36d2f4c510add /tools/perf/scripts/python/stackcollapse.py | |
| parent | 1b3b0bc2b3672e928e06997444528f8797579eb2 (diff) | |
PCI: qcom: Block accesses to downstream devices on link down
After a PCIe link goes down, software may still access the BAR (MMIO)
space or configuration space of devices behind that link before recovery
has run. As the link is down, these accesses never complete, resulting in
a storm of Completion Timeout AERs.
Use the controller's Outbound blocker to drop these accesses to the PCIe
address space as soon as the link-down interrupt fires, so that Completion
Timeout AERs are reduced. The blocked range covers the entire address
space (base 0x0, all-ones limit), since the Root Port's own DBI/iATU
register space remains accessible regardless.
The range is programmed once in the host init path, since the range
registers are wiped by BCR reset. This leaves only the OUTBOUND_BLOCKER_EN
bit to be flipped from the link-down IRQ handler, so the blocker can be
armed with a single fast register write for immediate effect.
The subsequent Root Port reset re-initialises the controller, which clears
the enable bit and re-programs the range for the fresh link.
Some IP revisions implement the Outbound blocker registers but do not wire
up the "global" interrupt used to deliver the link-down event that arms
the blocker, so there is no way to enable the blocker on those platforms.
Restrict blocker initialization to the post_init hooks of the IP
revisions that do have a global IRQ wired up
(qcom_pcie_post_init_2_3_3(), qcom_pcie_post_init_2_7_0() and
qcom_pcie_post_init_2_9_0()), instead of unconditionally programming it
from the common host_init path.
The link-down IRQ thread's blocker-enable write to PARF_SYS_CTRL can race
with a Root Port reset triggered independently through AER, which
reprograms PARF_SYS_CTRL as part of reinitializing the controller.
Serialize these with a per-controller mutex.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
[mani: renamed hw_lock to reset_lock, ECAM blocker to Outboound blocker, used guard(mutex)]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> # X1E80100 CRD + ASUS PA27AC
Link: https://patch.msgid.link/20260819-ecam_blocker-v2-1-e7a8fdc1c5cb@oss.qualcomm.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
