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| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2026-07-14 15:04:58 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-09-14 10:09:57 +0200 |
| commit | 971dcce966f519dc79cbd43d288587d13bdc6d58 (patch) | |
| tree | fbe7bf36d3986dd9d0c433a4561d234c2bb4aacd /tools/perf/scripts/python/stackcollapse.py | |
| parent | 0c3c3251e04cd9f5d45f75d8d10b8f17a417bdcc (diff) | |
arm64: dts: renesas: hihope-rzg2-ex: Specify ethernet PHY reset timings
The RTL8211E reference manual [1] page 38 chapter 7.16. PHY Reset
(Hardware Reset) states that the PHYRSTB pin must be asserted low
for at least 10ms (Tgap in Figure 10) and the system must wait at
minimum 30ms (for internal circuits settle time) before accessing
the PHY registers. Use 15ms and 35ms respectively to provide some
additional margin.
[1] https://files.pine64.org/doc/datasheet/pine64/rtl8211e%28g%29-vb%28vl%29-cg_datasheet_1.6.pdf
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260714130515.11262-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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